EEL4712T2Fall09 - EEL 4712 Digital Design Test 2 Fall...

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EEL 4712 – Digital Design Test 2 – Fall Semester 2009 Name ___________________________________ 1 IMPORTANT: Please be neat and write (or draw) carefully throughout the test. If we cannot read it with a reasonable effort, it is assumed wrong. As always, the best answer gets the most points . 1. Miscellaneous. (a) VGA display calculation: (b) For credit, show work . For Lab 6, assume the latency for the multiplier components is 6 clock cyles, the adders 10 clock cycles, and the rest of the datapath (memory, shift register, etc.) 7 clock cycles. Also assume that there are 10,000,000 words in the input stream (a new input word is inputted every clock cycle). The board clock frequency is 25 MHz. (4 points) How many nanosec before the first result is outputted? _____________ nsec How many clock cycles before the second result is outputted? ______________ clock cycles How many clock cycles before all the results are outputted? ___________________ clock cycles V id e o_ O n H or iz _ S y n c V e r t_ S y n c P ix e l in fo r m a tio n fo r 1 r o w (6 4 0 p ix e ls ) P ix e l in fo r m a tio n fo r 4 (o f 4 8 0 ) r o w s [4 x 6 4 0 p ix e ls ] 1 V e r t_ S y n c p u ls e fo r e a c h s c r e e n r e fr e s h 1 H o r iz _ S y n c p u lse fo r e a c h r o w r e fr e s h (4 8 0 r o w s p e r s c r e e n ) H S Y N C _ B E G IN H S Y N C _ E N D V S Y N C _ B E G IN V S Y N C _ E N D H _ D IS P L A Y _ E N D e tc . hcount = 0 vcount = 0 here D B E A A = 37.77 uS B = 3.77 uS D = 25.17 uS E = 0.94 uS For Lab 5, assuming the board clock frequency is 100 MHz, what constant should be use for H_DISPLAY_END? For credit, please show work. (For credit, show work here.) _________________ (answer) (4 pts.) 8 pts.
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EEL 4712 – Digital Design Test 2 – Fall Semester 2009 Name ___________________________________ 2 2. ASM and VHDL. (a) Shown in Figure 1(next page) is the VHDL specification of a ASM controller. Analyze the VHDL code and complete the following timing diagram: Specify the values for state (0, 1, 2, or 3), and outputs P, Q, Y, and Z. Note that there are two timing diagrams, each is independent of the other. For the last one, the initial state is given (as state = 3). Please show delays. 22 pts. 3
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EEL 4712 – Digital Design Test 2 – Fall Semester 2009 Name ___________________________________ 3 LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY T2Prob1 IS PORT ( Clock, Resetn, X, R, S : IN STD_LOGIC ; P, Q, Y, Z : OUT STD_LOGIC ) ; END T2Prob1 ; ARCHITECTURE Behavior OF T2Prob1 IS SIGNAL state : STD_LOGIC_Vector (1 DOWNTO 0); BEGIN PROCESS ( Resetn, Clock )
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EEL4712T2Fall09 - EEL 4712 Digital Design Test 2 Fall...

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