EEL4712T2Fall10 - EEL 4712 Digital Design Test 2 Fall...

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EEL 4712 – Digital Design Test 2 – Fall Semester 2010 Name ___________________________________ 1 1. Miscellaneous. (a) VGA display calculation: (c) There are 5 types of interconnects in the Cyclone FPGA family. Name 4 of them and give a one-sentence description of each. (4 pts) 8 pts. Video_On Horiz_Sync Vert_Sync Pixel information for 1 row (640 pixels) Pixel information for 4 (of 480) rows [4 x 640 pixels] 1 Vert_Sync pulse for each screen refresh 1 Horiz_Sync pulse for each row refresh (480 rows per screen) HSYNC_BEGIN HSYNC_END VSYNC_BEGIN VSYNC_END H_DISPLAY_END etc. hcount = 0 vcount = 0 here D B E A A = 37.77 uS B = 3.77 uS D = 25.17 uS E = ?? uS For Lab 5, assuming the board clock frequency is 100 MHz and the constant to be used for HSYNC_END is 2988, what is the time in uS (microseconds) for E? (For credit, show work here.) _________________ (answer) (4 pts.)
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EEL 4712 – Digital Design Test 2 – Fall Semester 2010 Name ___________________________________ 2 2. VHDL / ASM. Given the VHDL specification on the next page, (a) Draw the corresponding block diagram of the controller, showing the inputs and outputs. ( 2pts.) (b) Draw the corresponding ASM chart. (15 pts.) 17 pts.
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EEL 4712 – Digital Design Test 2 – Fall Semester 2010 Name ___________________________________ 3 ENTITY Prob2 IS PORT ( Clock, X, D1, D2 : IN STD_LOGIC ; Z1, Z2, Z3 : OUT STD_LOGIC ) ; END Prob2 ; ARCHITECTURE ASMArch OF Prob2 IS SIGNAL state : STD_LOGIC_Vector (1 DOWNTO 0); CONSTANT A : STD_LOGIC_Vector (1 DOWNTO 0):= "10"; CONSTANT B : STD_LOGIC_Vector (1 DOWNTO 0):= "01"; CONSTANT C : STD_LOGIC_Vector (1 DOWNTO 0):= "00"; CONSTANT D : STD_LOGIC_Vector (1 DOWNTO 0):= "11"; BEGIN Z1 <= '1' WHEN state = "10" AND D2 = '0' AND D1 = '0' ELSE '0'; PROCESS (state, D1, D2) BEGIN Z2 <= '0'; CASE state IS WHEN A => IF D1 = '1' AND D2 = '0' THEN Z2 <= '1'; END IF; WHEN C => Z2 <= '1'; WHEN OTHERS => END CASE ; END PROCESS ; PROCESS ( X, Clock ) BEGIN IF X = '0' THEN state <= A ; ELSIF (Clock'EVENT AND Clock = '1') THEN CASE state IS WHEN A => IF D2 = '1' THEN state <= A ; ELSIF D1 = '0' THEN state <= B; ELSE state <= C ; END IF ; WHEN “00” => IF D2 = '1' THEN state <= “10”; ELSE state <= D; END IF ; WHEN “01” => IF D2 = '1' THEN state <= B ; ELSE state <= “11”; END IF; WHEN OTHERS => state <= “10”; END CASE ; END IF ; END PROCESS ; WITH state SELECT Z3 <= ‘0’ WHEN “10”, ‘0’ WHEN C, ‘1’ WHEN OTHERS; END ASMArch ; VHDL code used for Problem 2.
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EEL4712T2Fall10 - EEL 4712 Digital Design Test 2 Fall...

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