EEL4712T2Fall2010Solution

EEL4712T2Fall2010Solution - EEL 4712 —- Digital Design...

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Unformatted text preview: EEL 4712 —- Digital Design Test 2 — Fall Semester 2010 1. Miscellaneous. amount f 0 (a) VGA dispzay calculation: :‘r’lgfgnt ‘ 0 VSYNC_END VSYNCkBEGlN Horiz_Sync Vert_Sync HSYNC_BEGIN ' H_DISPLAY_END HSYNC_END A: 37.77 uS B = 3.77 uS D = 25.17 uS E = ?? uS + I Horiz_.5'yrrc pulsefor each I Verr_Sync row refresh (480 pulse for each rows per screen) screen refi‘esh For Lab 5, assuming the board clock frequency is 100 MHz and the constant to be used for HSYNC_END is 2988, what is the time in uS (microseconds) for E? (For credit, show work here.) it g (answer) (4 pts.) [ff-frfirfl . : zzggr-tzmw aw ,9%fl§ (c) There are 5 types of interconnects in the Cyclone FPGA family. Name 4 of them and give a one—sentence description of e 4 pts) ach.( /’ LX/7m 7k flWf £15 /¢ 5W5, 27/} s 2 7% : /flfl; ._ I . . 7' Mex/fié fl : ,2 é’g/XX/a:27.$€a§ my _.— EEL 4712 - Digital Design Test 2 — Fall Semester 2010 Name 2. VHDL I ASM. Given the VHDL specification on the next page, (a) Draw the corresponding block diagram of the controller, showing the inputs and outputs. W (2pts.) x 2- / 7 P/ 22,7 ._,___ )2, w (b) Draw the corresponding ASM chart. (15 pts.) 223% x W EEL 4712 —- Digital Design . _ Test 2 — Fall Semester 2010 Name ENTITY Prob2 IS PORT ( Clock, X; D1, D2 : IN STD_LOG[C; ' Z1, 22, Z3 : OUT STD_LOGEC ) ; END Prob2 ; VHDL code used for Problem 2. ARCHITECTURE ASMArch 0F Prob2 IS SIGNAL state : STD_LOG|C_Vector (1 DOWNTO 0); CONSTANT A: STD_LOG|C_Vector (1 DOWNTO 0);: "10"; CONSTANT B : STD_LOGlC_VectOT (1 DOWNTO 0):: "01"; CONSTANT C : STD_LOGIC_Vector (1 DOWNTO 0):: "00"; CONSTANT D : STD_LOGIC_Vector (1 DOWNTO 0):: "11"; BEGIN » Z1 <= '1' WHEN state = "10" AND D2 = '0' AND D1 = '0' ELSE '0'; PROCESS (state, D1, D2) BEGIN Z2 <= ‘0'; CASE state [8 WHEN Am> IF [)1 = '1' AND D2 = '0' THEN 22 <= '1'; END IF; WHEN C => Z2 <= '1'; WHEN OTHERS => END CASE; END PROCESS ; PROCESS ( X, Clock) BEGIN IF X = '0' THEN state <= A; ELSIF (CIOCK'EVENT AND Clock = '1') THEN CASE state IS WHEN A => IF D2 = '1' THEN state <= A; ELSIF D1 = '0' THEN state <= B; ELSE state <= C ; END IF ; WHEN “00" => _ IF DZ = '1' THEN state <= "10"; ELSE state <= D; END IF ; WHEN "01" => IF [)2 = '1' THEN state <= B; ELSE state <= “11"; END IF; WHEN OTHERS => state <= "10"; END CASE ; END IF ; END PROCESS ; WITH state SELECT ZS <= ‘0' WHEN "10”; '0’ WHEN C, '1' WHEN OTHERS; END ASMArCh ; EEL Test 4712 — Digital Design 2 — Fall Semester 2010 Name 3. Cycione ll Logic Element (LE) Fryers 24. LE fr:- Ncrmai maze lN1 D... EB; gagmtershain nmnedmfi |N4 1:)— IN5 D" ““1 21 |N2 amp |N3 dams $5] Fiery. Column and fitmrxf l ml: Printing {in fifrom coal ‘ ’ cram-ow LE? |N5gredg§LAB Wide: . l 1:) 22 1 dam ‘1' enaiLAE Wide} IN3 aar {LAB was: Flegitcfer 86931393? Mfiflgiflk chain outfall? W Shown above isbcircuit diagram of a logic element (LE) in the normal mode, already "configured by Quartus”. Reverse-engineer it and draw the corresponding circuit diagram, as in a .bdf file. For a clear or set input, specify whether it is synchronous or asynchronous. Confnts f L T: Draw answer here: EEL 4712 —- Digital Design Test 2 - Fall Semester 2010 Name m 4.A|tSyncRAM veessevssszzeeé ..aisnc.:am1. '“g;‘sttgcggajag i'i'iinst “:- éI‘TIII'ZIZZI‘...IZ f1; aDATAInIT..0 bSimpleRDadddrF__o u..-, ‘i' '- Y bSimpleDualZU..0} A Einst14‘3‘05kT‘z‘l363MT0 ::::'::“:::.:: :.:.:: ramdatmif Complete the following timing diagram. Depth 2 256; - - «» Width=8; Assume all flip flops are initialized to 0 . Address—radix : hex; Both RAM’S has the same data (ramdatmif). ' Datagradix = hex; Content Begin 00 : 50; 07 : 57; 01 : 51; 08 : 58; 02 : 52; 09 : 59; 03 : 53; 0A: 5A; 04 : 54; DB : SB; 05 : 55; 0C : SC; 06 ; 56; etc. tips 5%;an liiillflns lfilliins militias 25316‘n5 mitts Mill-n5 tifllilins lfiflilifls Bllflilns 5591ilns 2257533 ' mil ..... . _____ ' ” “IF-33': .. .. .;. SlitglePeilZ a0; 1575? (a; 2: 52m); 3 {06%)}, 5 ~ a”ng ¢2KMQEQZ€9 . p. _ _ _ _ _ _ _ . . _ — . _ _ I _ _ . u . . . . w . — — __.. _ _ — — — — — — — — — _ 4 _ _ _ _ _ _ _ _ h _ w . . + . u . _ ._ I I . _ . . . . u — _ _ _ _ _ _ _ f _ _ _ . _ _ _ _ _ _ a _ .._r.-—.—————_-__-_——-—_____...-.--—'———l——————-———-———.l.————__________‘.______ litigant?" £€L--£€.€€Qi__é7_Q€:‘<2__§-__92fl3 ____ -_5§_:@a__@5&ezg_a2_z’w t I EEL 4712 — Digital Design [ngest 2 -— Fall Semester 2010 Name 5. Using altsyncram (configured as a true dual-port RAM) to implement a FIFO component. - FIFO wrreq, rdreq: block diaram - 00 or ‘ll: Output q[31..0] will hold the last value outputted from the FIFO - (disabling the flip-flop clocks) data-[31m {HST-*0] - 01: The next value in the FIFO will be outputed from the FIFO q[31..0] at wrreq the next active clock transition. rdreq - 10: data[31:0] will be written into the next empty location in the FIFO at the next active clock transition. empty empty: - I o 0: The FIFO is not empty (Some inputted values have not been outputted). 32 b'tX256 words a 1: The FIFO is empty. If a “rdreq” is asserted, then "junk" data will be outputted. aclr: asyncrhonous clear to “empty” the FIFO (a) Give me the VHDL statement(s) to produce the “empty” output; (3 pts.) 15—“ (b) Complete the design of the FIFO by making the required connections below using a true (g m5) dual-port altsyncram (For clarity, use labels when appropriate). Add any logic if necessary (for clarity, use logic expression like wrreq + rdreq instead of drawing gates). FIFO (design) data_a[31] aimmmzk I _1..o] data[31..0 W VT: if I ' dam-Pm-fi q[31l_0] rdreq — W 7 a] man, (- empty fifOClk — aclr — For altsyncramZ: o c|k_en = O disable flip-flop clocks 6 - clk_en = 1 enable flip-flip clock. EEL 4712 — Digital Design Test 2 — Fall Semester 2010 Name 6. You are to redesign the same FIFO component that was defined in Problem 5, now using a single—port altsyncram. Note that for this part, all the connections are made for you. All you need to do is to give me the ASM chart for the controller. FIFO (design) [2 data[31 ..0] _ (ti:- q[31..( Controller m n... Wan—mmlmm — 8-bit counter en1 q[7;0] aclr rdreq empty —— address[7..0] Clock 8—bit counter aclr For altsyncramt'. - clk_en = O disable flip-flop clocks - clk_en = 1 enable flip~fiip clock. Put the ASM chart for the controlller here: EEL 4712 ~— Digital Design Test 2 — Fall Semester 2010 7. FIR Filter Lab components is 7 clock cyles, the adders 5 clock cycles, and the rest of the datapath (memory, shift register, etc.) 15 clock cycles. Also assume that there are 10,000,000 words in the input stream (a new input word is inputted every clock cycle). The board clock frequency is 25 MHz. (3 pts) How many clock cycles before the first result is outputted? For credit, please show work. /5'/ 7%37’55'1‘9‘3’ g7 clockcycles (a) Assume an 8—tap FIR filter has the follOwing characteristics: the latency for the multiplier How many clock cycles before all the results are outputted? For credit, please show work. (2 pts) /flgflflflg C9 gé 3 7 7; [/p/fléW/wg .79 clock cycles (b) The above calculation assumes that all the components (adders and multipliers) can be “fully pipetined". if the design was not pipelined at all (i.e., we do not start on the next input until we completely finished the processing of the current input), how many clock cycles before _a_ll the results are outputted? (2 pts) (Show work) ; Z flflaz (95} fl clock cycles (c) Given the following decimal number -227.84375 (which is -11100011.11011 in binary), 7 convert it to the IEEE 754 floating-point format: (3 pts.) /.4Y Z" 1 a Bit 31: sign bit - Bits 30-23: exponent (with a bias of 127 = 111 1111 in binary) I n I . In . Eats 22 0. mantissa ,mgmw/a tea EIIEEEHEEIEEEEEE r HEEEEH ’rWW (d) The "range" for a number representation can be defined as the the difference between the maximum value and the minimum value that can be represented. Whereas the “precision” can be defined as the number of digits used to express the fractional part of a number. The more digits, the more precise. (4 pts) Order the following representations from the largest range to the smailest (circle number): - 32—bit fixed point (16.16) 1 2 Q . 64-bitfixed point (32.32) _ 1 @3 - IEEE single precision floating point @ 2 3 Order the following representations from the highest precision to the lowest: . 32-bit fixed point (16.16) 1 2 6‘) - 64—bit fixed point (32.32) Q 2 3 - IEEE single precision floating point 1 @ 3 Note: (16.16) means 16 bits used for integer part and 16 used for fractional part. ...
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EEL4712T2Fall2010Solution - EEL 4712 —- Digital Design...

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