EEL4712T2Fall2011Solution

EEL4712T2Fall2011Solution - EEL 4712 — Digital Design...

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Unformatted text preview: EEL 4712 — Digital Design Test 2 - Fall Semester 2011 \ Name 1. ASMNHDL. Given below is a timing diagram (functional simulation) showing the desired 18 pts timings among the states and signals of a controller. Name: E . we“ Resetn Clock _ _ ' State fiiif SA InBit 2;? BufFull ' ' ' ' ' ‘ ' i ‘ ‘ OutFlag 2UDDns EDDDns (a) Construct an ASM diagram that will produce the above behavior. (8 pts. ) 3 am; 9% 56,56 / W. 1.57%?" \ (b) Complete the VHDL specification (on the next page) of your ASM diagram. Please don't change the structure of the code. in other words, you have to use the first CASE statement to implement state transitions and the second CASE statement to implement the conditional and unconditional outputs. (10 pts.) ENTITY Test2P1 IS PORT ( Clock, Resetn. lnbit : IN STD_LOG|C ; -- Resetn is active low, asynchronous BufFull, OutFIag : OUT STD_LOG|C ) ; END Test2P1; EEL 4712 — Digital Design Test 2 -— Fall Semester 2011 Name 1(b) ARCHITECTURE ASMArch 0F Test2P1 is TYPE ASMstateType IS (SA, SB, SC) ; -- User defined signal type SIGNAL state : ASMstateType ; BEGIN PROCESS ( W] (M ) -— state transitions BEGIN EF Resetn — '0' THEN { <:: 5/? j I ELSiF( W W ALWMV) THEN CASE state IS WHEN SA => . , fitflgzfi'f: (fl 5%4‘L'59' 4:45; 5% ‘3 fé/‘ 54$ #3 WHEN SB => 5/5125 65%; WHEN SC => . //5 Jag/f —* ’0 'Zr/g/ 5% 059' [5? f/ ' {ES/f/° /F/' END CASE ; END IF ; END PROCESS ; ‘ PROCESS ( {1% , fig/f ) -- conditional and uncond. outputs BEGIN _ I . . dWor fax “WWW? 9’ . ' M 4 t a? ‘ CASE sta IS — You hage to use this CASE statement for the outputs. WHEN SA => We»? rs -" '/ ’2' - a .: #:ny if = wt was fl We; 5‘ f/VD HI) . .. WHEN 88 => 4 3 ' ’ - fi/M // K WHEN so => END CASE ; END PROCESS ; END ASMArch ; EEL 4712 — Digital Design Test 2 — Fall Semester 2011 Name 2. Given the following circuit: 20 pts. |N1 - (synchronous) CLEAR I (synchronous) LD D CLOCK - D =|N10llN2 + Z 2 (a). Complete the following VHDL specification for it. (6 pts) LIBRARY ieee ; USE ieee.std_logic_1164.ai| ; ENTITY Test2LEprob 18 PORT ( lN1, IN2, CLEAR, LD , CLOCK: IN STD_LOG|C ; -- synchronous Z : OUT STD_LOG|C ) ; -- CLEAR, LD END Test2LEprob ; 0 0 hold 0 1 load ARCHITECTURE LEArch OF Test2LEprob IS 1 X clear SIGNAL WE fi/fl,Mé/c ) BEGIN PROCESS [6444(6) BEGIN —— for maximum credit, all your code should be inside this PROCESS statement. //:/flfl6/KW flw flfl‘h 1/ y raza/ //3 Caz/M —" ‘/ ’ 77%?/ 5'24: W ‘/‘ f5”: 49: '/ ’ 777254/ @224: LM aw Mfi/fflyflfl Wé* KW #3:), EM? //j‘ 26: END PROCESS; END LEArch ; EEL 4712 -— Digital Design Test 2 — Fall Semester 2011 Name 2(b). You are to “program” the logic element (LE) of an Altera Cyclone ll device to implement the circuit from the previous page (from Problem 3). in other words, for each “location” (A through L), specify what should be connected to it. it can be 0, 1, X (“don’t care”), or a signal name (like CLEAR). If it is "don’t care”, you must put X (not 0 or 1). Also specify the contents of the LUT (look up table). (14 pts) (assume ngfifs 2-3. if in News! Mada W 1N1 E)— '1? 1N2 D 52:" R .13 h 1 age rc am LD D— ccnnection CLEAR |:>-— l CLOCK D— (H) 0 - B fipwfiglummzir 2 (fig; dam-1 mm m M“ Saw”... r UiieclLinlc Re lN1dam x2 Y “dwewcciummam X (K) dalag - Foulkmpufi 5 I Eittectijnk Routing - . 00s LUT “W cm {from emit 301 : X3 WWW LE) lune (Ehmtmewsae; '% gmmm D Z |N2 dismal X4 (F) ens (“LAB Wide] ' 0 (G) aolrtLABWide) (I) 9/ /' Register 113.. ff... zit-5'"; .z - ,.c§}fi\.c{' FothLCJ'. chair} Qutput Put your answers here. Each signal should be connected to O, 1, X (“don’t care”), NC (for not connected), or a signal name. if it is “don't care”, you must put X (not 0 or 1). g I w (a m (B) gear/M (F) x2 (J) (G) WEE: (C) (D) (H) EEL 4712 —‘ Digital Design Test 2 — Fall Semester 2011 Name 3. AltSynRam Timing 19 pts' ; 33 35 i 2? 3 Z 5 f i E ii 3 i 3 E ; : i" 7 ::::::::::“""' ::::"""""""§aa ,: : édta a__Oltncram2 256 Wordts} RAM ‘ ‘ ‘ ,, ,, ,";<;;,agck ___ 1 , , “a; ;;CL;o¢i<‘iinsnsfiéockwpezmo Depth=256; Width = 8; Address_radix = hex; Data_radix = hex; Content Begin DO : 70; OT : 77; 01 : 71; 08 : 7'8; 02 : 72; 09 : 7'9; Complete the following timing diagram. Assume all flip-flops are initialized to ‘0'. Both RAM’s has the same data (ramdatmif). ' ' 03: 73; 0A : 7A; 04 : 74; DB : 7B; 05: 75; 00 : 70; g 06: 76; § 5 a ‘U w I I l aWRai g l i i . 22 bDfliTAln g , " u bAddi ;; bWRen = ' ; as: éfiiéiieiii at, iiiiéiilalii E23:23?:[i@}£’éi2?€fi?i """"""""""" " Please put values in hex and an “X” where the value changes for SinglePortZ, aTrueDuaiZ, and bTrueDualZ. 5 EEL 4712 — Digital Design Test 2 -— Fall Semester 2011 Name ifiiiiii begin W fl X My} 5;! rue/om?“ 4. Testbench for GCD Calculator Lab. Given below is the testbench for the GOD calculator. library ieee' . . . ’ . _ entity gcd 13 use ieee.std_logic__1164.all, generic ( use leee.numenc__std.a||; WIDTH : positive := 16},- entity gcd_tb is Port { end gcd tb; clock : in stdwlogic; . _ . reset : in std_logic; architectureTB ofgcdftbisy. I I go : in Std—logic; constant WIDTH .poSItIve .=32, done ; out sthOgiC; 00n3tant TIMEOUT 3 tlme 3: 1 m5; a: in std_1ogic_vector(WIDTH—l downto 0) ; signal clkEn :std_logic :='1‘; b: in std_1ogic_vector(WIDTH-1 downto 0); output: out stdfilogic_vector(WIDTH—1 downto 0)); signal cik : std_logic := '0'; signal rst : std_logic :2 '1'; signal go : std_iogic := ‘0'; signal done : std_|ogic; signal x : std__iogic_vector(WiDTH-1 downto O) := (others => '0'); signal y : std_logic_vector(WiDTH-i downto 0) := (others => '0'); signal output : std_logic_vector(WlDTH—l downto 0); end gcd; (a) Explain: , UUT:entity work.gcd(FSlVlD) What“work" indicates? ' - 'M m 24% W wfiév 4% What “Fit/lg: indi ates/g ‘fi'mm m Aé2&égér (day /flfl¢¥%flflé¢ /£:SZ¢%2:>. (b) Put the PORT MAP statement here to “connect” the entity gcd to the testbench. Note that some signal names in god (clock, reset; a, and b) have been changed. par MW” / 4%, W s? garage?“ 31> M .. :7 ‘ fifb a. a; x)- clk <= not clk and clkEn after 20 ns; process function GCD (x, y : integer) return std_|ogic_vector is variable tme, tmpY : integer; begin tme := x; tmpY := y; while (tme I: tmpY) loop if tme < tmpY then tm pY := tmpY-tme; else tme := tme-tmpY; endifi endloop; return std_logic_vector(to_unsigned(tmpX, WIDTH»; end GCD; (c) How is the GCD function used in this testbench? 6 EEL 4712 — Digital Design Test 2 — Fall Semester 2011 Name begin . . I I (d) Explain the function of loop l and clkEn <= 1 ; this statement. rst <= '1'; t go <= IOI; x <2 std_logic_vector(to_unsigned(0, WIDT y <= std_logic__vector(to_unsigned(0, WID ’ wait for 200 ns; rst <= ‘0'; for i in 0 to 5 loop wait until cik'event and clk = '1" end loop; -- i tori in 1 to 2**WlDTH-1 loop x <= std_logic_vector(to_unsigned(i, WIDTH»; forj in 1 to 2**WlDTH—1 loop go <: l1l; y <= std_logic_vector(to_un 'ned(j, WIDTH wait until done = '1' for TIMEO ‘; assert(done = '1') report "Done ne )) r asserted. severity warning; go <= IOI; d |wraituntil clk'event and clk = 1'; (e) Explai the function of loop and en Oop' this stat ment. end loop; clkEn <= '0'; report "DONEllllll" severity note; wait; end process; end TB; (f) Put back an assert statement here to verify that the input values produce a correct output. . ‘ if U '- W/fiwe WfiKafj/yw W - =- W. 2 (Q) How many bits are the input/output signals? 97; 7 EEL 4712 — Digital Design Test 2 — Fall Semester 2011 Name 5. FIR filter ASIIII problem 18 pts. FIFO Used by other ' _ component { da.ta[31..E}] q[3-'I " (not used for I this test) “- "Sq rdreq empty This simple dual-port RAM replaces the Input ROM In Lab 6 to produce Input[31..0] to FIR Filter. to Lab 6 FIR Filter Input Connected{ 32 bits :4 255 wotds _ - I ' [31..0] CtrCl-R _’ Address wradddress CHEN _, Generator . Other Controller ' Controller controner OUtDUtS Filter Synchronous: Inputs - CLR clears counter Start 0 EN increments counter dock You are to design the controller of following component to fill the Input RAM for a Lab 6 FIR filter (from Location 0 to Location 256). Note that the input RAM plays the same role as the Input ROM in Lab 6. o The controller will wait until it receives a RDY = “I” from the Lab 6 FIR filter, then it will proceed to fill the Input RAM. 0 It will check to see if the FIFO is empty - If empty = ‘1', it wlII wait. a if empty=‘0’, o It will request a 32—bit value from the FIFO (set rdreq = ‘1'). The next value in the FIFO will be outputed from the FIFO qi31..0] at the next active clock transition. - This value should be written into the next location in the Input RAM. 0 This will be done until the Input RAM is full (256 locations), each time making sure the FIFO is not empty. 0 When finished, it will signal the Lab 6 FIR filter by setting Start = ‘1' and return to the Wait state. Note: Function of the FIFO: 0 rdreq: - 0: The output q[31..0] will hold the last value outputted from the FIFO. 0 1: The next value in the FIFO will be outputed from the FIFO q[-3‘l..0] at the next active clock transition. o empty: 0 0: The FIFO is not empty (there are some values in it). o I: The FIFO is empty. EEL 4712 — Digital Design Test 2 — Fall Semester 2011 Name 5. continued (a) Complete the block diagram ofthe Controller, specifying all the Controller inputs and Controller outputs (3 pts.) W (b) Put the ASM chart for the Controller here. (15 ptsfljoy’ Li ‘ EEL 4712 — Digital Design Test 2 ~ Fall Semester 2011 Name 6. VGA lab 9 pts. 3. RED. GREEN. BLUE l i |*— C —'*i D "HF—*F—E—‘i HORlzJBYNC Figure 1. Horizontal Refresh Cycle. Given above is the horizontal refresh cycle for the VGA lab. Define the following: 'FlED, GREEN? BLUE m l"—Q—*| Ft —*l4—b —*l VEFTLSYNC i~—P—-i | Figure 2. Vertical Refresh Cycle. O——-——+—-—-*-~—-—’I Given above is the horizontal refresh cycle for the VGA lab. Define the following: EEL 4712 — Digital Design Test 2 - Fall Semester 2011 Name ENTITY _entity_name IS PORT(__input_name, _input_name : IN STD_LOGIC; _input_vector__name : IN STD_LOGEC_VECTOR(_¢_hIgh downto ___low); _bldirw_name. _bidir_name : INOUT STD_LOGIC; _output_name, _output_name : OUT STD_LOG]C); END _entity_name; ARCHITECTURE a OF _entity__name IS SIGNAL ___signal_name : STD_LOGIC; SIGNAL __signa|_name : STD_LOGIC; BEGIN -— Process Statement —— Concurrent Signal Assignment —- Conditional Signal Assignment —— Selected Signal Assignment —— Component Instantiation Statement END 3; SIGNAL w__signzll_name : ___type_name; ____instance_name: _component_name GENERIC MAP (__component_par =>_connect__par) PORT MAP (__component_port => wconnectvport, _component_port => _connect__port); WITH _expression SELECT ___signal <= _expression WHEN __constent_value, _expression WHEN __constant_va|ue, __expression WHEN __constant_value, _expression WHEN moonstant_value; _signal <= _expression WHEN _boolean__expression ELSE ___expression WHEN mbooleanfiexpression ELSE _expression; IF __expression THEN “statement; "statement; ELSIF __expression THEN “statement; __statement; ELSE __statement; _statement; END IF; <generate_label>: FOR <|00p_id> IN <range> GENERATE -- Concurrent Statement(s) END GENERATE; WAIT UNTIL _expression; CASE _expression' IS WHEN flco'nstanLvalue => __statement; mstatement; WHEN _constant_value => "statement; __statement; WHEN OTHERS => _statement; _statement; END CASE; .11 ...
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EEL4712T2Fall2011Solution - EEL 4712 — Digital Design...

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