FinalExamFall09Solution

FinalExamFall09Solution - EEL 4712 —- Digital Design...

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Unformatted text preview: EEL 4712 —- Digital Design Final Exam —— Fall Semester 2009 Name lMPORTANT: Please be neat and write (or draw) carefully. If we cannot read it with a reasonable effort, it is assumed wrong. Smail8-related groblem: Shown below is a modified architecture of the 's'rh'éii'a' '¢'or'm5tité'r'fAssuriie' that all the components are the same as you had them in your mini—project with the following exceptions: - The outputs of AR, PC, SP, and IX are connected to the External Address Bus through a set of 4—to-1 MUX’s. o The RAM is a 64K X 8 asynchronous RAM. The timing requirements of its read and write operations are given in the timing diagram on the next page. - There is a flag register cailed tempC (temporary carry), with synchronous LD and CLR. - Registers Tempi and Temp2 are connected as shown, both with synchronous LD and synchronous CLEAR inputs. 4-t0-1 MUX’S 64K X 3 As nch RAM AR PC ExAD[15..D] (External Address Bus) AD[15..0] SP [X ‘ Din[7..0] ExData[7..D} (External Data Bus) 8 Dout[7..0] A31 A30 MemEN LDen V A STen MemOE MemWE Internal Bus ARH ARL PCH PCL SF’H SPL IXH IXL 16 AR 16 16 PC 16 SP IX Synchronous LD: all registers and flipflops Synchronous CLR: IX, Tempt, Temp2, tempC OE (output enable): ARH, ARL, PCH, PCL, JXH, IXL INC (increments the 16—bit register by 1): PC, SP. DEC (decrements the 16-bit SP register by 1): SP. CFIag Also, there is a 3~bit counter with synchronous no 8 “MEN masts... COUNTER . CIn of the ALU ___> CLR MUX selects CT_7 which carry EN " goes to the ALU-OE Y controller (See next page for ALU functions) EEL 4712 — Digital Design Final Exam — Fall Semester 2009 Name Timing requirements for the read and write operations of the asynchronous RAM: CLK I I I I I I I I I Dout outdaéa MemEN - I MemOE MemWE Read outdata Write indata from Ioc. 0101 to too. 0104 Functions 000 Zero (F = 0) 001 Add with carry (F = X + Y + Cin) Subtract (X—Y) with borrow (F = X + [Y + Cin)* Shift right (F = x >> 1), Cin>>F7, F0>>Cout Shift left (F = x << 1), F0<<Cin, Cout<<F7 tot Bit—wise XOR (F = x XOR Y) Bit-wise AND (F = x AND Y) Bit-wise OR (F = x OR Y) ALU functions * The Cin for subtraction is the borrow input. 1. You are to implement the following two instructions for the Small8 computer by completing the ASM chart on the next page: Description INCA (FA) A <= (A) + i; Increment Register A. a Note that A is just a storage register. You cannot directly increment Register A. o Affects only the Z and 8 flags. ADA $addr (D0) mem($addr) <= mem($addr) + (A) + (C); 0 Add the content of RegisterA to some content in memory (in location $addr) - For example ADA $0070 will add the content of Register A to memory location $0070. - Register A should retain its original value. c All 4 flags are affected. EEL 4712 — Digital Design Final Exam — Fall Semester 2009 1. (continued) Complete the following ASM chart. Note that you do not have to complete the Name __________________ opoode fetch state. For maximum credit, use the minimum number of states (including the use of conditional -- -- -- outputs). For maximum partial credit,_“comment” your..A.SM. chart. " Fetch opcode" PCJNC opoode For ease of grading, use the following notation. For example: CSl.CSO = 01 ALU.SEL = 101 A81,ASO = 10 FA INCA D0 ADA $addr 44mww/ ivy/fa / $455949 (24,, / flza fl; x4! AP , 2”. AP ’ J/ W EEL 4712 — Digital Design Final Exam — Fall Semester 2009 Name 2. Small8 Program Execution— at the clock cycle level - Given the following .mif file and use the architecture shown in Page 1. The opcodes for the instructions can be found in the instruct-ion set-sheet - -- -- -- - - The initial values of memory locations: 2000 = 90, 2001 = 91, 0102 = 72, 0108 = 78, 0109 = 79. (All values are in hex.) If any initial values are not specified, assume it is 0. Analyze the above .mif file and specify the content of each of the register or memory location (in hex). Note that each row in the table below represents the contents at the end of each clock cycle. All values should be in HEX. For ease of grading, draw an arrow to indicate no change to a register lanai: Man ea vs; mum m II III- l IE '5 lil 07/); = gy— EEL 4712 ~— Digital Design Final Exam — Fall Semester 2009 Name 3. Address decoding for SmallB: - ' INPORT W5” vfl/¢»/?/;v/_r7§ vW-flm - fl7 «fig/9’? 7%,; disc/54' fi—flzvflfl M i ,47. w 4K X 8 RAM_A film-0.7 A[11..0] pizza] 011.0] W WE «———- /F— '- 0E writ - e fijj/ Mama M3 fir; ‘ (a) Not counting index addressing, how many inflame can load the data from INPORT to Register A? Give me one of them. (2 pts.) fXXOA Xxxx KKK/g4 Xxx“ A. How many? Give me one figflpa é, g r' .1 (b) Make the appropriate connections to OUTPORT so that only STAA $4F07 will write the contents of Register A to OUTPORT. (4 pts.) (0) Make the apprOpriate connections to the RAM such that LDAA $5000 will access the first location in the RAM and LDAA $5FFF will access the last location in RAM-A. (4 pts.) d/& /,t (2054, &004, air/w B" fl/fl/fl 7’_///,t ////A //r 1 You should draw on the figure above and may use any AND gates that you need. As always, for maximum credit, use the minimum number of gates. 5 EEL 4712 — Digital Design Final Exam - Fall Semester 2009 Name 4. VHDL Analysis (timing diagrams): Given the following VHDL specification, complete the following timing diagram for outputs 2(0), 2(1), 2(2), 2(3). LIBRARY ieee ; USE ieee.stdmlogic_1164.all ; ENTITY P'io'bii 'I'S' ' PORT ( 'D, CLOCK, RESETn, CLRn : lN STD_LOGIC; Z : OUT STD_LOGIC_VECTOR(0 TO 3) ) ; END Prob4 ; ARCHITECTURE P4ArCh OF Prob4 !8 BEGIN 2(a) W PROCESS CLOCK, RESET . BEGIN ( n) :0 fly” IF RESETn = '0' THEN 2(0) <= '0'; ELSIF CLOCK'EVENT AND CLOCK=‘1' THEN IF CLRn = '0' THEN 2(0) <= '0'; ELSE 2(0) <= D; END IF; END IF; END PROCESS; PROCESS (CLOCK) BEGIN IF CLOCK='I' THEN 2(1) <= D; END IF; END PROCESS; \ M PROCESS (CLOCK) W BEGIN 2 M ‘2” ’4? IF CLOCK'EVENT AND CLOCK='1' THEN 2(2) <= D; END IF; END PROCESS; ‘ PROCESS (D;CLOCK) BEGIN IF CLOCK='1' THEN 2(3) <= D; 'mpmant N019: . END “:1 a Every flip-flop is initialIzed to ‘0' and latch END PROCESS; starts off with an M value. END P4ArCh ; 0 Please Show propagation delays. EEL 4712 — Digital Design Final Exam — Fall Semester 2009 Name 5. VHDL Analysis (circuit synthesis). Given the following (“non—sense”) VHDL specification, draw the circuit diagrams for the Corresponding components. Draw them on the next page. ""LIBR'A'RY iee'e ; USE ieee.std_|ogic_1164.all ; ENTITY TestP5 IS PORT (A, B, c, D, E, G, L£CLK : IN STD_LOG|C; J : lNOUT STD_LOG|C; Y ‘. lNOUT STD_LOGIC_VECTOR (2 DOWNTO 1) ); END TestP5 ; ARCHITECTURE P5Arch OF TestPS IS COMPONENT ch PORT (A: IN STD_LOG|C; x1, X2: OUT STD_LOG|C); END COMPONENT; SIGNAL TEMP1,TEMP2,TEMP3: STD_LOG]C; BEGEN PROCESS (A, C, E, TEMP1. CLK) BEGIN IF E = '0' THEN TEMP2 <= A; ELSE TEMP2 <= C; END IF; lF TEMP1 = '0' THEN Y <= "00"; ELSIF (CLK'Event AND CLK = '1') Y(2) <= Y(1); CASE B. is WHEN '0' => Y(1) <= TEMPB; WHEN OTHERS => Y(1) <= D ; END CASE ; END lF; END PROCESS ; ch port map(X1 =>J, X2 =>TEMP3, A =>TEIVIP2); TEMP1 <= G WHEN l = '0' ELSE J; END P5Arch ; EEL 4712 — Digital Design Final Exam — Fall Semester 2009 Name Problem 5: Put your answer here. . .zéfm..... 6. VHDL s ecification ProbSCircuit 8—bit Shift Register (SR) 0 PG has a D flip—flop with synchronous LD and CLR. CLR has priority over LD. - SR is a 8—bit shift register: If SHF = 1, it will synchronoust shift right, else “hold”. n p— — 1F 27;?) =4 3 W 1'4» 27—.» (XMM - 5/7/4457“ 3’ Jar/70 g7 EEL 4712 — Digital Design Final Exam — Fall Semester 2009 Name Problem 6: Put your answer here. 0 Complete the VHDL code below. The best answer gets the most goints. - o All your code in the architecture must be inside the one PROCESS statement. ENTITY ProbGCircuit 54? - ---- ----PORT(-SHF, - ,--iNlT,-CL-K:|N STD_LOG|C;- . D :EN STD_LOGOC_VECTOR (7 DOWNTO 0); 20, P : OUT STD_LOGIC); END ProbBCircuit; ARCHITECTURE behaviorArch OF ProbBCircuit SiGNAL f? 57:0,.M6/(L Vf/VOfl[/;WMV/0 (7)2“ _ $3; fiwwmwa- Véfmxé’)‘ BEGlN PROCESS( 6' 1&0? / -- All your code must be inside this m PROCESS statement. I; (ct/ZY’ZVéfifl/W amt": V ,3) WW 1/: //V/7-‘-‘- I/I 7flE/V '59”; 525/er" L9 = '/’ 7745” were 72%;; 2M) m9 227% dflflflj /F £531.} 7 ’/ ’ 724/Efl/ W’ZJPJ [Li/F 5/; v 7’ 7746/ pg? 11% a 705 MW” 77/7 2/0 «4: WQW 0; £QLMWC % iffl<rv3 imvfi? £azrf'é%%5 /7 é: WW; END PROCESS; END behaviorArch; EEL 4712 — Digital Design Final Exam — Fall Semester2009 Name _-__________________ 7. Digital design using ASM: An 8—bit parallel—to-serial (P-S) converter circuit, the block diagram of which is shown in Figure 7(a), is to be designed with the foilowing specifications (as illustrated in the timing diagrambelow in Figure.7.(b)i . o If the Reset signal is asserted ‘1', the ASM is asynchronously reset to the initial state. I c As long as the START input is ‘0’, the P-S converter remains in an idle state in which it outputs a 't’ at SOUT (called a Mark (M) bit). c When this START input is '1’, |N[7..DO] is loaded into the shift register and a ‘0' (called a START bit) is outputted at SOUT, - In subsequent clock cycles, ZE?..0] is shifted out, starting with 2(0) and ending with 2(7). 0 After Z[7..0] have been shifted out, a Parity bit (P) is outputted. P is the output of the Parity Generator (PG) circuit, followed by a '1’ (called a Stop bit). - Ideally, we would like to shift the data out one byte right after another (along with the Start, Parity, and Stop bits) without any Mark bits if the START is continuously ‘1'. Otherwise, Mark bits will be inserted between bytes. Parallel-to-Serial (PS) Converter Controller START Counter Reset CountEQ? Counter is a 3- bits chronous counter. When count = "111", then CountEQT <= ‘1’. Both CLR and EN are synchronous. CLK (used as clock signal for all components) Figure 7(a). Block diagram design of the PS converter. 7 1 byte of data_ CLK SOUT M: M ‘ NI EM EStartg zo 21 Z2é 23E 24E 25 26327 EPBFiWEStOPE an bu bu M: Mark bit If another byte is ready, this would be a Start bit (0). Otherwise, this would be a Mark bit (1). Figure 7(b). Timing diagram illustrating the behavior of the PS converter. 10 EEL 4712 ~ Digital Design Final Exam — Fall Semester 2009 Name 7. Answers for Problem 7 here. (a) What signals from the Controller need to be connected to the LD and CLR of the D flip-flop - in the Parity Generator? (2 pts.) - ---------L-D= f/ffifl CLR= JAE/W (b) in this part, you only need is to produce the ASM chart for the controller of the PS Converter. The best answer gets the most points. In other words, using less states and conditional outputs to improve performance will result in more points. However, it is better to get a correct answer with more than minimum states than to get an erroneous answer with fewer states. (16 pts. ) Put your ASM chart here: flefigf 64/? W fl 7’ {fl/flrs/fi' / M/W%§/Wj Problem: Points: 1 {15 pts) 2 (16 pts) 11 Total: 100 ...
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FinalExamFall09Solution - EEL 4712 —- Digital Design...

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