FinalExamFall10 - EEL 4712 Digital Design Final Exam Fall...

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EEL 4712 – Digital Design Final Exam – Fall Semester 2010 Name ___________________________________ 1 IMPORTANT: Please be neat and write (or draw) carefully. If we cannot read it with a reasonable effort, it is assumed wrong. Small8-related problem: to be used for Problems 1, and 2. Shown below is a modified architecture of the Small8 computer. Assume that all the components are the same as you had them in your mini-project, plus the following: SP is a 16-bit Stack Pointer Register (SPH and SPL). Note SP is not shown below. The outputs of AR, PC, SP, and IX are connected to the External Address Bus through a set of 4-to-1 MUX’s. The RAM is a 64K X 8 asynchronous RAM. The timing requirements of its read and write operations are given in the timing diagram on the next page. There is a new flag register called tempC (temporary carry). Registers Temp1 and Temp2 are connected as shown, both with a syncrhronous LD input and a synchronous CLR (clear) input. B is a 16-bit general purpose register, BH is the high byte, BL is the low byte. 8 Temp1 A D Temp2 ALU A.OE D.OE T2.OE Cout C tempC CFlag CSEL C 0 1 tempC Cin CS1 CS0 (To Controller) 00 01 10 11 0 1 T1.OE Temp1 MUX selects the input to the Cin of the ALU ff ff MUX selects which carry goes to the controller X Y F Note: There is also a 16-bit Stack Pointer SP register (not shown) Synchronous LD : all registers and flipflops OE (output enable): PCH, PCL, SPH, SPL, IXH, IXL, BH, BL, Temp1,Temp2, D, A INC (increments the 16-bit register by 1): PC, SP, AR DEC (decrements the 16-bit SP register by 1): SP CLR (synch. clear): Temp1, Temp2, all flip-flops ExData[7. .0] (External Data Bus) ExAD[15. .0] (External Address Bus) Internal Bus ARH ARL AR BH BL B AD[15. .0] Din[7. .0] Dout[7. .0] MemEN MemOE MemWE 64K X 8 Asynch RAM LDen STen SP IX PC AR 00 01 10 11 AS1 AS0 4-to-1 MUX’s PCH PCL PC IXH IXL IX 8 8 8 8 16 16 16 16 16 Note the connections to the MUX’s
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EEL 4712 – Digital Design Final Exam – Fall Semester 2010 Name ___________________________________ 2 1. You are to implement the following two instructions for the Small8 computer by completing the ASM chart on the next page: LDSI <data> and STDB <addr>. $89 $00 $41 $90 $00 $24 CLK ExAD Din Dout MemEN MemOE MemWE 0101 0102 0103 0104 0105 ZZ indata ZZ ZZ outdata ZZ Read outdata Write indata from loc. 0101 to loc. 0104 Timing requirements for the read and write operations of the asynchronous RAM: LDSI $4100 STDB $2400 $1050 $1051 $1051 $2300 $2301 $2302 $2400 $2401 Opcode/description example LDSI <data> (89) Load SP with two LDSI $4100 bytes stored immediately after the op code.
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FinalExamFall10 - EEL 4712 Digital Design Final Exam Fall...

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