FinalExamFall10Solution

FinalExamFall10Solution - . . __ h \ EEL 4712 - Digital...

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Unformatted text preview: . . __ h \ EEL 4712 - Digital Design W Finat Exam — Fall Semester 2010 Name " W IMPORTANT: Please be neat and write (or draw) carefully. If we cannot read it with a reasonable effort, it is assumed wrong. SmaIIB-reiated problem: to be used for Problems 1, and 2. Shown below is a modified architecture of the SmallS computer. Assume that all the components are the same as you had them in your mini-project, plus the following: a SP is a 16-bit Stack Pointer Register (SPH and SPL). Note SP is not shown below. 0 Theoutputs of AR, PC, SP, and IX are connected to the External Address Bus through a set of 4—to—1 MUX’s. ‘- The RAM is a 64K X 8 asynchronous RAM. The timing requirements of its read and write operations are given in the timing diagram on the next page. 0 There is a new flag register called tempC (temporary carry). - Registers Temp1 and Temp2 are connected as shown, both with a syncrhronous LD input and a synchronous CLR (clear) input. a B is a 16-bit general purpose register, BH is the high byte, BL is the low byte. Note the connections 440-1 to the MUX’s 64K X a MUX’S SP Asynch RAM [X ExAD[15..O] (External Address Bus) PC AD[15..O] AR Din[7..0] ExData[?..0] (External Data Bus} DouttT..0] A81 A80 MemEN ALDEN v A STE]? MemOE Internal Bus MemWE 16 AR 16 PC 16 B 16 IX Note: There is also a 16-bit Stack Pointer SP register (not shown) Synchronous LD: all registers and ftipf/ops OE (output enable): PCH, PCL, SPH, SPL, lXH, iXL, BH, BL, Temp1,Temp2, D, A INC (increments the 16-bit register by 1): PC, SP, AR DEC (decrements the 16—bit SP register by 1): SP mag CLR {synch clear): Tempt, Temp2, at! flip-flops (To Conlroiler) MUX selects the input to the Ci'n of the ALU MUX selects * which carry goes to the 72.05 controller i x - EEL 4712 — Digital Design Final Exam -— Fall Semester 2010 Name Timing requirements for the read and write operations of the asynchronous RAM: Write lndata to inc. 0104 Read outdata from Ice. 0101 1. You are to implement the following two instructions for the Small8 computer by completing the ASM chart on the next page: LDSI <data> and STDB <addr>. Opcodeldescription example LDSI <data> (89) Load SP with two LDSI $4100 bytes stored immediately after the op code. STDB <addr> (9.0) Store value from 16-bit STDB $2400 (new register 8 to two bytes Assume Reg B = $17A1; instruction) Then after STDB $2400 - mem ($2400) = 3A1 - mem ($2401) = $17 in memory: mem($addr) mem ($addr + 'l) EEL 4712 — Digital Design Final Exam — Fall Semester 2010 Name 1. (continued) Complete the following ASM chart for the following two instructions. Note that you - d; not have to complete the opcode fetch state. For maximum credit, use the minimum number of states (including the use of conditional outputs). For maximum partial credit, “comment” your ASM chart. “Fetch opcode" PCJNC EEL 4712 — Digital Design Final Exam — Fall Semester 2010 Name 2. Compiete the following part of the ASM diagram to My implement the LDAA b,X instruction. For maximum credit, optimize your ASM diagram. To refresh your memory, the LDAA b,X is 14 pts‘ a 2—byte instruction and is defined as follows: - A <= MEM(EA) where EA is the “effective address" EA = IX + b where ix is the 16—bit content of the IX register and b is the "offset" byte. stored next in memory after the LDAA b,X opcode. . Ex: If ix: $20FF; b= $05. Then EA: $20FF + $0005 = $2104 (Hint: 16-bit addition) Important Notes: - [X is a 16—bit storage register; with a LD input (cannot be incremented or do addition). a For the ALU: 82,81,80 = 110 means F = X plus Y plus Cin; Cout is the carry out. a You cannot use "user" registers and flags (i.e., A, D. C flag) for the implementation of an instruction like LDAA b,X. More Notes: Both C and tempC flags are fiipflops whose inputs are from the Cout of the ALU. Both the C and tempC have synchronous LD and CLR inputs. ‘ (You don't have to "Fetch OPCOGB" implement the opcode PCJNC fetch state.) (For maximum partiat credit, “comment” your ASM diagram.) A 2—byte Instruction: Ware far/{7,4} M a 7 _ few/c. 4/? 6. EEL 4712 r— Digital Design Final Exam — Fall Semester 2010 Name 3. Assembly language program and .mif file (a) Given the following .mif file, analyze it and produce the corresponding assembly ' language program. All addresses and contents are in hex. (8 pts) Put the corresponding assembly program here: 422% We L—#——-———-— 5" 72;? .29 \\ flees? 1.1:? XI $5252 72 AfiWfl $2, X flfiw .D {We .5» LE 2%: X 3/ 450% fax E—x—h—q fizz/i9 D 57.21,? grew-=5" Assume locations $0070 through $0079 contains the following data. (Note you don't have to produce the assembly statements for the data.) 1% ariawz s 4%ng; J7 5' fflfl r:- .— flz’ a 3 We" a my. (b) Briefly explain the function of the program (a co‘uple of sentences). (5 pts.) My Z 52/72 7° #2 : fay-7;; / W a” a 5/ : «aw; {M9 ~ What is in Ougufltlzogrt 0 at thegend of the program? flflwflflé EEL 4712 - Digital Design Final Exam — Fall Semester 2010 Name 4. Generic component using GENERATE statement (a) Give the (non-generic) code required to implement the PE (processing element) component (in one PROCESS block): (5 pts.) d ENTITY PE IS PORT (ci, oin, clk, aclr : IN STDMLOGIC; Qout :OUT STD_LOGlC ); 00‘” END PE; ARCHITECTURE behavior OF PE IS SIGNAL Wag as” BEGIN -- give the answer in one PROCESS block; fiéoéét ) PE component PROCESS ( % BEGIN- [F £534., P 'fl 'm’éw J» ,4 _ 97'; fj/f; 4"" V ,2 F ‘ [AS/F gm ’é’yé/wf ma“? 5% r / ) flew 7/2}? 4%: fim 5MP m; _ fW/d: de- 7%? W?) END PROCESS: END behavior ; (b) Complete the following code (Both ENTlTY and ARCHITECTURE sections to implement the following generic genericPEs component. CF(n) genericPEs component h _ _ _ _ — — u u u ~ _ _ — — — — — — — n _ n _ _ _ _ _ — — — — — u u _ _ — — _ — — — p u _ _ _ — — — u _ h — —._J ENTITY genericPEs l8 (2 pts) GENERlC(n: INTEGER :=4); D _ PORT(Xxy}7’ 5%] flgfaf I/V {aléflé/zf, 3/7? I” 5W~M5£Vézmen fox/z); ism/fr W7 {7% mm; ) ; END genericPEs; EEL 4712 — Digital Design Final Exam — Fail Semester 2010 Name 4(b) continued a Complete the foltowing Architecture section. You have to use GENERATE and PORT MAP statements. (6 pts) ARCHETECTURE struct OF genericPEs IS COMPONENT PE IS PORT (Ci, Qin, clk, aclr : IN STD_LOG|C ; Qout : OUT STD_LOG|C ) ; END COMPONENT; SIGNAL 4 57?.Zflé/fwb/é‘gfégfl f 5*” 232/952 BEGIN 47/0 {I >6“; )' [KM] Fifi ,4“ 1745/ 1/ 7a m ' I fail flfl/E’V 1/37}??? ( (4' 1-) (lg-(Vii)! 5'7 §[4'~/)/ afixy% “19% :7 M, -§M37@4‘)); aw _.MWM,¢ n2”; M6: fl MI); END struct; EEL 4712 — Digital Design Final Exam -— Fall Semester 2010 5. VHDL I ASM. - Given the VHDL specification on the next page, (a) Draw the corresponding block diagram of the controller, showing the inputs and outputs. Name .EEL 4712 — Digitat Design Final Exam — FaII Semester 2010 Name ENTITY Prob5 18 PORT( Clock. X1. X2, X3 : IN STD_LOGIC ; Z1, 22, 23 : OUT STD_LOGIC }; END Prob5 ; VHDL-code used for Problem 5. ARCHITECTURE ASMArch OF Prob5 IS SIGNAL state : STD_LOGIC_~Vect0r (1 DOWNTO O)" CONSTANT A : STD_LOG|C__Vect0r (1 DOWNTO 0):: "00"; CONSTANT B : STD__LOGIC_Vect0r (1 DOWNTO 0):: "01"; CONSTANT C I STD_LOGIC_VeCt0r (1 DOWNTO 0):: "10"; CONSTANT D I STD_LOGIC_Vect0r (1 DOWNTO 0):: "11"; BEGIN 21 <= '1' WHEN state = "00" AND X3 = '0' AND X2 = '0' ELSE '0'; PROCESS (state, X2, X3) ' BEGIN Z2 <= '0‘; CASE state IS WHEN A => IF X2 = '1' AND X3 3 ‘0' THEN Z2 <= '1'; END IF; WHEN C => 22 <= '1'; WHEN OTHERS => END CASE ; END PROCESS; ' PROCESS ( X1, Clock ) -— State transitions BEGIN IF X1 = '0' THEN state <= A ; ELSIF (CIock'EVENT AND CIock = '1') THEN CASE state IS WHEN A => IF X3 = '1' THEN state <= A; ELSIF X2 = ‘0' THEN state <= B; ELSE state <= C ; END IF ; WHEN "10” => IF X3 = '1' THEN state <= "00"; ELSE state <= "1 1"; END IF ; WHEN “01" => _ IF X3 = '1' THEN state <= B; ELSE state <= “11”; END IF; WHEN OTHERS => ' state <= "00”; END CASE ; END IF ; END PROCESS ; WITH state SELECT Z3 <= ‘0’ WHEN “00“, ‘0' WHEN "10", ‘1’ WHEN OTHERS; END ASIVIArch ; EEL 4712 — Digital Design Final Exam —- Fall Semester 2010 Name 6. Address decoding RAM-A D7-DO A9-A0 ‘ - OE CEB fl/fi' r flM-flx/ «fl/flgflf, - A15-A0 —> if V? ya/fé *flféflg a _ oroo flfi pgg°flffiflfl’ Law: A10-A0 - 4—-—-> 2—to-4 Decoder D7-D0 R_w CEC . O = LDAA A11 CED CED :D_ 1 = STAA A10 CBC CEB' 1A15 AND IA14 , CEA A8-A0 AB—AO AND IA13 AND A12 D7-DO CEA CE Given the memory configuration shown above: M f/ 47 (a) What is the size of RAM—A122 X g RAM—B? Z X 6’ RAM-C? 2 X5“ (b) What is the 16-bit address of the first location in RAM-A? fiflfl/A /&fl& flflflé’ may (in binary) figfiQGn hex) (c) What is the 16—bit address of the fast location in RAM-A? 0&5’4 /p//4 ////4 //// (in binary) (in hex) (d) What are all the 16-bit addresses of the first location in RAM-C (in hex)? ' WWW (e) What are all the 16—bit addresses of the last location in RAM-C (in hex)? 5W? x x w J/ii’ Hr; ates fume: a; fi/Ffl: (f) Make the appropriate connections (and logic) to INPORT so that any of the following instructions (and only those addresses) will load data from INPORT to register A: LDAAFF, LDAA WFF, LDAA ssIFFF, or LDAA sjiFFF. f’E/fi/aw 0/6?!) 5379/ aflfl fix! / “:72? fl/XX 10 EEL 4712 * Digital Design Final Exam — Fall Semester 2010 Name 7. ASM design Hardware Stack Module MEM (simple dual mode) ‘ altsyocramtt i5! 5-: a r-r . c 73.9 DATAI7..0] 4 2.0.1.93", wwwwww mm ’ EEDEEPJE mgr fiéihitfns if?) 013:1 ..c] OE Controller CLK OP[1..O] ADDR[7..O] (etc. you can add more controller outputs if necessary) You are to design the controller (ASM chart) for this Hardware Stack Module. The functions of the Stack Module are as foElows: 93 Function _ 0 0 Disabled: DATA[7..0] are tri-stated. 0 1 PUSH operation: SP <= SP + 1; then MEM(SP) <= DATA[7..O]; 1 0 POP operation: MEM(SP) is outputted at DATA[7..O]; then SP <= SP — 1; 1 1 DEFINE new SP: SP <= DATA[7..0] Important notes: - The altsynram is configured to be in the "simple dual port" mode. 0 Note that DATA [7.0] is bi-directional and altsynram has a separate data in (data[7..0]) and data out (q[7.,0]). You have to design something to take care of this, including adding more outputs to the controller. 0 For MEM, “men” is the write enable. and “clock enable" enabtes the clock and the synchronous-loading of all flip—flop in the altsyncram. (a) Make all the necessary'connections in the figure above (for neatness, use labels when possible). You can also use any necessary gates. (b) Draw the ASM chart for the Controller on the next page. 11 EEL 4712 — Digital Design Final Exam — Fali Semester 2010 Name 7(b). Put the ASM Chart for the soiution of 7(b) here: ‘— '2 V .. - S W > Problem: Points: - r 12 ‘ Total: 100 ...
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FinalExamFall10Solution - . . __ h \ EEL 4712 - Digital...

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