lab2fall11 - Lab 2: MSI Combinatorial Components and VHDL...

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Lab 2: MSI Combinatorial Components and VHDL EEL 4712 – Fall 2011 1 Objectives: The objective of this lab is to use VHDL to specify the designs and testbenches for various MSI combinatorial components. You will also explore the new features in Quartus, ModelSim, and the UF- 4712 board. Required tools and parts: Quartus II software package, ModelSim-Altera Starter Edition, UF-4712 board. Important: For this and the subsequent labs, put your name and section number as a comment at the beginning all VHDL files and other materials that you submit. Pre-lab requirements: 1. Specify in VHDL the following 4-to-1 MUX: Note that the MUX has an active low enable EN and an active low output Y. So, you must specify your VHDL code accordingly. Use a SELECT signal assign statement or a conditional signal assignment statement. Modify the provided testbench (mux4to1WithAssert_tb) and perform a timing simulation. Turn in on e-Learning: all VHDL files; a screenshot of the ModelSim transcript window that show “Simulation Finished” without any assertion errors. Printout for your TA: the design of the MUX (.vhd file) and the timing simulation results. Note that you do not have to print out the simulation result of all possible combinations of the inputs, only some representative samples. 2. Design and simulate a display “decoder” for using the 7-segment LED displays on the UF-4712 board. The logic table for the display “decoder” and the corresponding display are shown below: You can use any VHDL statements to implement the display “decoder”, including simple signal assignment statements . Note that the LEDs on the UF-4712 board are active low.
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lab2fall11 - Lab 2: MSI Combinatorial Components and VHDL...

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