lab3fall11 - Lab 3: 8-bit Behavioral ALU EEL 4712 Fall 2011...

Info iconThis preview shows pages 1–2. Sign up to view the full content.

View Full Document Right Arrow Icon
Lab 3: 8-bit Behavioral ALU EEL 4712 – Fall 2011 (Rev 1) 1 Objective: The objective of this lab is to create an 8-bit ALU using behavioral VHDL, whose output is shown on the two 7-segment LEDs. The data inputs to the ALU are connected to the two DIP switches, and the select input is connected to the 4 buttons. In this lab, you will become familiar with the arithmetic VHDL package numeric_std. In addition, you will get experience using test benches to verify the correct functionality of the circuits you specify in VHDL. Required tools and parts: Quartus2 software package, ModelSim-Altera Starter Edition, UF-4712 board. Pre-lab requirements: 1. Create an 8-bit adder using a behavioral architecture with the numeric_std package. The entity and architecture must appear in the a file named adder8numeric.vhd and have this exact specification: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity adder8numeric is port(input1, input2 : in std_logic_vector(7 downto 0); carry_in : in std_logic; sum : out std_logic_vector(7 downto 0); carry_out : out std_logic); end adder8numeric; You can use the testbench in Lab2 (adder8_tb.vhd), with appropriate modifications, to simulate adder8numeric. Turn in on e-Learning:
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 2
This is the end of the preview. Sign up to access the rest of the document.

This document was uploaded on 03/05/2012.

Page1 / 3

lab3fall11 - Lab 3: 8-bit Behavioral ALU EEL 4712 Fall 2011...

This preview shows document pages 1 - 2. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online