Lab 4: VGA Signals and Color Raster Picture
EEL 4712 – Fall 2011
The objective of this lab is to study the generation of the control signals required by a VGA monitor
by creating a component VGA_sync_gen that generates those signals. Using VGA_sync_gen and
additional components, a simple color raster image will be displayed on a VGA monitor.
Required tools and parts:
QuartusII software package, UF-4712 board, and VGA Monitor.
Altera Cyclone II EP2C8T144C8 FPGA, Quartus altsyncram component, brom.mif.
An altsyncram component will be used in this lab, which requires memory that is available only on
the device such as the Cyclone II EP2C8T144C8 FPGA. All output bits of this lab should be directed to
the appropriate pins of the UF-4712 VGA connector. Also, a memory initialization file (brom.mif) will be
used to initialize the memory values of the ROM.
UF-4712 Board Manual
The VGA monitor connector on the UF-4712 board consists of five signals, RED, GREEN, BLUE,
HORIZ_SYNC, and VERT_SYNC. Look into the UF-4712 Board Guide for the header pin outs for the UF-
4712 board for these 5 signals.
The timing relationships among this signal are shown in
Figures 1 and 2
at the end of this lab write-up. The generation of signals needed for the raster on the VGA monitor begins
with dividing the frequency of the 25.175 MHz clock on the UF-4712 board down to the horizontal and
vertical sync frequencies.
This means your design will contain a
. The horizontal and vertical synch pulses of appropriate lengths are then produced from the two
Horizontal and vertical synchronization. A video display consists of 640 pixels in the horizontal
direction and 480 lines of pixels in the vertical direction. The monitor starts each refresh cycle by updating
the pixel in the top left-hand corner of the screen, which can be treated as the origin (0,0) of an X–Y
plane. After the first pixel is refreshed, the monitor refreshes the remaining pixels in the row. When the
monitor receives a pulse on the
pin, it refreshes the next row of pixels. The time required
for the sweep, the horizontal sweep period, is nominally 31.77
This process is repeated until the
monitor reaches the bottom of the screen. When the monitor reaches the bottom of the screen, a 64
pulse applied to the
pin, causing the monitor to begin refreshing pixels at the top of the
screen (i.e., at [0,0]). As shown in Figure 2, the VERT_SYNC pulse must be repeated every 16.6 ms
(vertical sweep period).
A complete screen of information is being traced by the electron beam every
16.6 ms for a frame rate of 60 Hz.
Blanking intervals. In order to accommodate the time required to move the electron beam back to