lab6FIRFall11 - Lab 6: FPGA Parallel Processing Techniques...

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Unformatted text preview: Lab 6: FPGA Parallel Processing Techniques FIR Filter Design EEL 4712 Fall 2011 1 Objective: The objective of this lab is to study parallel processing techniques for the design and implementation of a finite impulse filter (FIR) on an FPGA. An algorithmic state machine is used to control a data path component to exploit parallelism through functional decomposition, replication, and pipelining. Required tools: UF-4712 board, Quartus II Design Software, altfp_mult megafunction (floating-point multiply), altfp_add_sub megafunction (floating-point add), altsyncram megafunction, and Quartus In-System Memory Content Editor Discussion: Filters are signal conditioners by accepting an input signal, blocking some specified frequency components, and passing the input signal minus those components to the output. Finite impulse response (FIR) filters are one of the most common types of digital filters used in Digital Signal Processing (DSP) applications. A brief introduction to FIR filters can be found in the article Introduction to Digital Filters . The basic structure of a FIR filter consists of a series of multiplications followed by an addition, as represented by the following equation: ( ) = ( ) ( ) = 0, 1, 1 =0 In this equation, x(k) represents the sequence of input samples, y(k) is the output, a(n) represents the filter coefficients, and N is the number of taps. Note that an FIR filter simply produces a weighted average of its N most recent input samples. All the magic is in the coefficients (a(n)), which dictate the actual output for a given pattern of input samples. To design a filter means to select the coefficients (or generate the coefficients using a software package like MATLAB) such that the filter has specific characteristics (e.g., low-pass, band-stop, or high-pass). An outline of an implementation of an N-tap FIR filter, written in C and based on the above equation, is given in the article Introduction to Digital Filters . Note that it is basically a FOR loop . A hardware design of an 8-tap filter based on the equation is illustrated in Figure 1. Each register (Ri) provides a unit sample delay (i.e., shift registers). Each output stage of a particular register is multiplied by a known coefficient. The resulting outputs of the multipliers are then summed to create the filter output. Note that the FOR loop of N iterations in the C program has been unrolled into N filter output....
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lab6FIRFall11 - Lab 6: FPGA Parallel Processing Techniques...

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