lab7Fall11 - Lab 7: Three-state Buffer, Bus, and RAM EEL...

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Lab 7: Three-state Buffer, Bus, and RAM EEL 4712 – Fall 2011 1 Objectives: The objectives of this lab are (1) to study the use of 3-state buffers in the implementation of buses and (2) to study the functions of RAMs. The tasks performed in this lab are in preparation for the design and implementation of the Small 8 computer in subsequent labs. Pre-lab requirements: 1. Storage registers with 3-state buffer outputs: Specify a VHDL behavioral description of an 8-bit wide 3-state buffer shown in Figure 1. This component can be used to connect the outputs of various components to a bus as described in Section 7.14.1 of the textbook. Specify a VHDL behavioral description of an 8-bit storage register , with a synchronous LD input (and no built-in 3-state buffers). Specify a VHDL behavioral description of an 8-bit storage register , with a synchronous LD input and built-in 3-state buffers . When EN is true, then Q is connected to D. Otherwise, Q is in a high- impedance state. Compile and simulate the three components and verify their functions individually. Integrate the three components to implement the design in Figure 1 using structural VHDL (PORT MAP statements). Perform a functional simulation verifying all the functions of the circuit. Turn in eLearning: All VHDL code (designs and testbenches) and simulation results for the three components and the circuit in Fig. 1. 2. Switch debouncing and clock divider circuits. We will use one of the push button on the UF-4712 board as a “single-step” clock signal. In order to use the push button as a clock signal, it must be debounced so that a single push of the button results in only one clock edge. As described in class, one technique to debounce a switch signal S is to shift the bouncing signal down a shift register. The debounced signal DB_S is the output of an AND gate ANDing the outputs of the flip-flops of the shift register. Assume the bounce interval of a switch has been experimentally determined to be about 3 ms.
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lab7Fall11 - Lab 7: Three-state Buffer, Bus, and RAM EEL...

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