ProcessSequentialStatementsPartA

ProcessSequentialStatementsPartA - 1 PROCESS statement (...

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Unformatted text preview: 1 PROCESS statement ( contains sequential statements) Simple signal assignment statement <= Variable assignment statement := IF-THEN-ELSE statement WAIT UNTIL statement CASE-WHEN statement FOR-LOOP and WHILE-LOOP statements Syntax: [process_label] PROCESS (sensitivity_list) [VARIABLE declaration] BEGIN sequential statements END PROCESS [process_label]; Sensitivity list : When there is a change in the value of any signal in the sensitivity list, the process becomes active . Active : when a process block becomes active, the statements inside the process block are evaluated sequentially: at synthesis time (determine what circuit to build), not at run-time (not like a program running inside a microprocessor). 2 LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY Dflipflop IS PORT ( D, LamClk : IN STD_LOGIC ; Q : OUT STD_LOGIC) ; END Dflipflop ; ARCHITECTURE Behavior OF Dflipflop IS BEGIN PROCESS ( LamClk ) BEGIN IF LamClk'EVENT AND LamClk = '1' THEN Q <= D ; END IF ; END PROCESS ; END Behavior ; Figure 7.37 Code for a D flip-flop LamClkEVENT: EVENT is an attribute of the signal LamClk, which becomes TRUE when there is any change in the LamClk signal. When a condition in the form of LamClk'EVENT AND LamClk = '1' " is found in an IF statement, any signals that are assigned values inside the IF statement are implemented as the outputs of edge-triggered components (i.e., flip-flips). 3 Figure 7.39 D flip-flop with asynchronous reset LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY flipflop IS PORT ( D, Resetn, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC) ; END flipflop ; ARCHITECTURE Behavior OF flipflop IS BEGIN PROCESS ( Resetn, Clock ) BEGIN IF Resetn = '0' THEN Q <= '0' ; ELSIF Clock'EVENT AND Clock = '1' THEN Q <= D ; END IF ; END PROCESS ;...
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This document was uploaded on 03/05/2012.

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ProcessSequentialStatementsPartA - 1 PROCESS statement (...

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