SnippetMultiDimGenerate - reg(0 is the input to the...

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-- Snippet of code to demonstrate Multi-dimensional arrays and GENERATE statement ARCHITECTURE struct OF datapath IS -- Definition of other components COMPONENT multiplier IS PORT ( clock : IN STD_LOGIC; dataa : IN STD_LOGIC_VECTOR(31 DOWNTO 0); datab : IN STD_LOGIC_VECTOR(31 DOWNTO 0); result: OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END COMPONENT; CONSTANT coe1: STD_LOGIC_VECTOR (31 DOWNTO 0):=x"3D824326"; CONSTANT coe2: STD_LOGIC_VECTOR (31 DOWNTO 0):=x"3F034080"; CONSTANT coe3: STD_LOGIC_VECTOR (31 DOWNTO 0):=x"3F034080"; CONSTANT coe4: STD_LOGIC_VECTOR (31 DOWNTO 0):=x"3D824326"; SUBTYPE signalVectors IS STD_LOGIC_VECTOR(31 DOWNTO 0); TYPE array4OfSignals IS ARRAY(4 DOWNTO 1) OF signalVectors; TYPE array5OfSignals IS ARRAY(4 DOWNTO 0) OF signalVectors; SIGNAL coeff: array4OfSignals; SIGNAL reg: array5OfSignals; -- reg(4 DOWNTO 1) are outputs of the 4 registers
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Unformatted text preview: -- reg(0) is the input to the flip-flop with the most recent data SIGNAL mout: array4OfSignals; BEGIN coeff(1) <= coe1; coeff(2) <= coe2; coeff(3) <= coe3; coeff(4) <= coe4; reg(0) <= Input; -- shift register code mults: FOR i IN 1 to 4 GENERATE multArray : multiplier PORT MAP (clock=>clk, dataa=>coeff(i), datab=>reg(i), result=>mout(i)); END GENERATE mults; -- mult1: multiplier PORT MAP (clock=>clk, dataa=> coeff(1), datab=>reg(1), result=>mout(1)); -- mult2 : multiplier PORT MAP (clock=>clk, dataa=>coeff(2), datab=>reg(2), result=>mout(2)); -- mult3 : multiplier PORT MAP (clock=>clk, dataa=>coeff(3), datab=>reg(3), result=>mout(3)); -- mult4 : multiplier PORT MAP (clock=>clk, dataa=>coeff(4), datab=>reg(4), result=>mout(4)); -- code for adders END struct;...
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