Lab11.315 - nominal Q-point corresponding to your design,...

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EECE-315 Prelab 11 In this lab, you will be verifying the JFET bias design that you did in the homework problem. 1. Check back to the homework problem and record the values of all components used in the bias circuits, including the supply voltage. 2. Also record the PSpice values of the worst-case maximum and minimum DC drain current.
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EECE-315 Lab 11 1. Use a 2N3819 JFET to build up the bias circuit that you designed. Measure I DQ , V GSQ , and V DSQ . Make sure that you measure all resistance values. 2. Use a curve tracer to find the I DSS and V P (at least 2 significant figures) of your 2N3819 JFET. Print a hard copy. Add a load line to the curve tracer plot and show the
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Unformatted text preview: nominal Q-point corresponding to your design, and the measured Q-point. 3. Use the measured I DSS , V P and resistance values to calculate the theoretical I DQ , V GSQ and V DSQ . Compare them to the measure values in step (1). 4. Perform the following three cases, and discuss your results (Refer to Table I of your design homework). R 1 R 2 R S Measured I DQ Case I Nominal Nominal 5% higher (using a decade resistance box) Case II Nominal 5% higher (using a decade resistance box) Nominal Case III 5% higher (using a decade resistance box) Nominal Nominal...
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This note was uploaded on 03/11/2012 for the course ECE 185 taught by Professor Ma during the Spring '12 term at CSU Chico.

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Lab11.315 - nominal Q-point corresponding to your design,...

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