Chapter 09 - Interrupts

Chapter 09 - Interrupts - Chapter 9 Interrupts 1996 1998...

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Chapter 9 – Interrupts 1996 1998 1982 1995
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BYU CS/ECEn Chapter 9 - Interrupts 2 Topics to Cover… n Interrupts n Interrupt Service Routines (ISR’s) n Example 9.1 – Watchdog ISR n Processor Clocks n Example 9.2 – Master Clock n Low Power Modes n Example 9.3 – Low-Power Mode n Timers n Example 9.4 – Interrupts w/Timer_A n Watchdog Timer n Example 9.5 – Watchdog Clock n Pulse Width Modulation (PWM) n Example 9.6 – LED PWM w/Timer_A n Speaker (Transducer) n Example 9.7 – Speaker PWM w/Watchdog
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BYU CS/ECEn Chapter 9 - Interrupts 3 n Who produces the trash? n Who empties the trash? Main Routine Interrupt Service Routines Disable Interrupts Global Variable Interrupt Service Routine Interrupt Service Routine
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BYU CS/ECEn Chapter 9 - Interrupts 4 Interrupts n Execution of a program normally proceeds predictably, with interrupts being the exception. n An interrupt is an asynchronous signal indicating something needs attention. n Some event has occurred n Some event has completed n The occurrence of an interrupt is unpredictable. n Processor stops with it is doing, n stores enough information to later resume, n executes an interrupt service routine (ISR), n restores saved information, and then n resumes execution. n Interrupts preempt normal code execution n Interrupt code runs in the foreground n Normal (e.g. main() ) code runs in the background n Event-driven programming n The flow of the program is determined by events—i.e., sensor outputs or user actions (mouse clicks, key presses) or messages from other programs or threads. n The application has a main loop with event detection and event handlers Interrupts
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BYU CS/ECEn Chapter 9 - Interrupts 5 Interrupt Flags n Each interrupt has a flag that is raised (set) when the interrupt is pending. n Each interrupt flag has a corresponding enable bit – setting this bit allows a hardware module to request an interrupt. n Most interrupts are maskable , which means they can only interrupt if 1) Individually enabled and 2) general interrupt enable (GIE) bit is set in the status register (SR). n Reset and Non-Maskable Interrupts (NMI) are reserved for system interrupts such as power-up (PUC), external reset, oscillator fault, illegal flash access, watchdog, and illegal instruction fetch. Interrupts Device Interrupt Interrupt Enable General Interrupt Enable (GIE) Interrupt MPU Reset / Non-maskable (NMI)
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BYU CS/ECEn Chapter 9 - Interrupts 6 Interrupt Vectors n The CPU must know where to fetch the next instruction following an interrupt. n The address of an ISR is defined in an interrupt vector . n The MSP430 uses vectored interrupts where each ISR has its own vector stored in a vector table located at the end of program memory. n Note: The vector table is at a fixed location (defined by the processor data sheet), but the ISRs can be located anywhere in memory.
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Chapter 09 - Interrupts - Chapter 9 Interrupts 1996 1998...

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