--csci5221-router-design

--csci5221-router-design - Router Design Overview of...

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CSci5221: Router Design 1 Router Design • Overview of Generic Router Architecture • Input-Queued Switches (Routers) • IP Address Look-up Algorithms • Packet Classification Algorithms Readings: Do required readings (you can skip the math in Section V and Appendix in [Mc+99]); Also do some of the optional readings if interested
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CSci5221: Router Design Routers in a Network .
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CSci5221: Router Design 3 Sample Routers and Switches Cisco 12416 Router up to 160 Gb/s throughput up to 10 Gb/s ports 3Com 4950 24 port gigabit Ethernet switch Juniper Networks T640 Router up to 160 Gb/s throughput up to 10 Gb/s ports
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CSci5221: Router Design 4 High Capacity Router • Cisco CRS-1 – up to 46 Tb/s thruput • two rack types • line card rack – 640 Gb/s thruput – up to 16 line cards • up to 40 Gb/s each – up to 72 racks • switch rack – central switch stage – up to 8 racks • in-service scaling
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CSci5221: Router Design Components of a Basic Router • Input/Output Interfaces (II, OI) – convert between optical signals and electronic signals – extract timing from received signals – encode (decode) data for transmission • Input Port Processor (IPP) – synchronize signals – determine required OI or OIs from routing table • Output Port Processor (OPP) – queue outgoing cells • shared bus interconnects IPPs and OPPs CP IPP OPP . II OI routing table output queue Control Processor (CP) » configures routing tables » coordinates end-to-end channel setup together with neighboring routers
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CSci5221: Router Design 6 Generic Router Architecture Lookup IP Address Update Header Header Processing Address Table Lookup IP Address Update Header Header Processing Address Table Lookup IP Address Update Header Header Processing Address Table Queue Packet Buffer Memory Queue Packet Buffer Memory Queue Packet Buffer Memory Data Hdr Data Hdr Data Hdr 1 2 N 1 2 N
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CSci5221: Router Design 7 Switch Fabric: Three Design Approaches
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CSci5221: Router Design 8 Switch Fabric: First Generation Routers Traditional computers with switching under direct control of the CPU Packet copied to the system’s memory Speed limited by the memory bandwidth (two bus crossings per packet) Input Port Output Port Memory System Bus
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CSci5221: Router Design 9 Shared Memory (1 st Generation) Route Table CPU Buffer Memory Line Interface MAC Line Interface MAC Line Interface MAC Typically < 0.5Gbps aggregate capacity Limited by rate of shared memory Shared Backplane
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CSci5221: Router Design 10 Switch Fabric: Switching Via a Bus Packet from input port memory to output port memory via a shared bus Bus contention: switching speed limited by bus bandwidth 1 Gbps bus, Cisco 1900: sufficient speed for access and enterprise routers (not regional or backbone)
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CSci5221: Router Design 11 Shared Bus (2 nd Generation) Route Table CPU Line Card Buffer Memory Line Card MAC Buffer Memory Line Card MAC Buffer Memory Fwding Cache Fwding Cache Fwding Cache MAC Buffer Memory Typically < 5Gb/s aggregate capacity; Limited by shared bus
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CSci5221: Router Design 12
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--csci5221-router-design - Router Design Overview of...

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