Lect2UP030_(100324)

Lect2UP030_(100324) - Lecture 030 DSM CMOS Technology...

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Lecture 030 – DSM CMOS Technology (3/24/10) Page 030-1 CMOS Analog Circuit Design © P.E. Allen - 2010 LECTURE 030 - DEEP SUBMICRON (DSM) CMOS TECHNOLOGY LECTURE ORGANIZATION Outline • Characteristics of a deep submicron CMOS technology • Typical deep submicron CMOS technology • Summary CMOS Analog Circuit Design, 2 nd Edition Reference New material Lecture 030 – DSM CMOS Technology (3/24/10) Page 030-2 CMOS Analog Circuit Design © P.E. Allen - 2010 CHARACTERISTICS OF A DEEP SUBMICRON CMOS TECHNOLOGY Isolation of Transistors The use of reverse bias pn junctions to isolate transistors becomes impractical as the transistor sizes decrease.
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Lecture 030 – DSM CMOS Technology (3/24/10) Page 030-3 CMOS Analog Circuit Design © P.E. Allen - 2010 Use of Shallow Trench Isolation Technology Shallow trench isolation (STI) allows closer spacing of transistors by eliminating the depletion region at the surface. p + pp - Metal Salicide n - n n + Oxide Poly 070330-03 Polycide Gate Ox n + n -well n + p -well n + Substrate n + Shallow Trench Isolation n + Shallow Trench Isolation Shallow Trench Isolation p + p + n + Substrate Salicide Well Salicide Decreased spacing Substrate Salicide S hal low Trench Isolation I s o l ati n Sha llow Trench Lecture 030 – DSM CMOS Technology (3/24/10) Page 030-4 CMOS Analog Circuit Design © P.E. Allen - 2010 Comparison of STI and LOCOS What are the differences between a LOCOS and STI technology? Comments: • If the n + to p + spacing is large, the Bird’s beak can be compensated using techniques such as poly buffered LOCOS • At some point as the n + to p + spacing gets smaller, the restricted bird’s beak leads to undesirable stress effects in the transistor. • An important advantage of STI is that it minimizes the heat cycle needed for n + or p + isolation compared to LOCOS. This is a significant advantage for any process where there are implants before STI.
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Lecture 030 – DSM CMOS Technology (3/24/10) Page 030-5 CMOS Analog Circuit Design © P.E. Allen - 2010 Shallow Trench Isolation (STI) 060203-01 Nitride Silicon (1) (2) (3) (4) (5) (6) 1.) Cover the wafer with pad oxide and silicon nitride. 2.) First etch nitride and pad oxide. Next, an anisotropic etch is made in the silicon to a depth of 0.4 to 0.5 microns. 3.) Grow a thin thermal oxide layer on the trench walls. 4.) A CVD dielectric film is used to fill the trench. 5.) A chemical mechanical polishing (CMP) step is used to polish back the dielectric layer until the nitride is reached. The nitride acts like a CMP stop layer. 6.) Densify the dielectric material at 900°C and strip the nitride and pad oxide. Lecture 030 – DSM CMOS Technology (3/24/10) Page 030-6 CMOS Analog Circuit Design © P.E. Allen - 2010 Illustration of a Deep Submicron (DSM) CMOS Technology n + p -substrate Metal Layers NMOS Transistor PMOS Transistor 031211-02 M1 M2 M3 M4 M5 M6 M7 M8 0.8 μ m 0.3 μ m 7 μ m Deep n -well Deep p -well n + STI p + p + STI STI Salicide Polycide Salicide Polycide Sidewall Spacers Salicide Source/drain extensions Source/drain extensions
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Lect2UP030_(100324) - Lecture 030 DSM CMOS Technology...

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