Lect2UP040_(100324)

Lect2UP040_(100324) - Lecture 040 UDSM and BiCMOS...

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Unformatted text preview: Lecture 040 UDSM and BiCMOS Technologies (3/24/10) Page 040-1 CMOS Analog Circuit Design P.E. Allen - 2010 LECTURE 040 - ULTRA-DEEP SUBMICRON AND BiCMOS TECHNOLOGIES LECTURE ORGANIZATION Outline Ultra-deep submicron CMOS technology- Features- Advantages- Problems BiCMOS technology process flow- CMOS is typical submicron (0.5 m) Summary CMOS Analog Circuit Design, 2 nd Edition Reference New material Lecture 040 UDSM and BiCMOS Technologies (3/24/10) Page 040-2 CMOS Analog Circuit Design P.E. Allen - 2010 ULTRA-DEEP SUBMICRON (UDSM) CMOS TECHNOLOGY USDM Technology L min 0.1 microns Minimum feature size less than 100 nanometers Todays state of the art:- 65 nm drawn length- 15 nm lateral diffusion (35 nm gate length)- 1.2 nm transistor gate oxide- 8 layers of copper interconnect Specialized processing is used to increase drive capability and maintain low off currents Lecture 040 UDSM and BiCMOS Technologies (3/24/10) Page 040-3 CMOS Analog Circuit Design P.E. Allen - 2010 65 Nanometer CMOS Technology TEM cross-section of a 35 nm NMOS and PMOS transistors. NMOS: PMOS: These transistors utilize enhanced channel strains to increase drive capability and to reduce off currents. P. Bai, et. Al., A 65nm Lobic Technology Featuring 35nm Gate Lengths, Enhanced Channel Strain, 8 Cu Interconnect Layers, Low-k ILD and 0.57 m 2 SRAM Cell, IEEE Inter. Electron Device Meeting , Dec. 12-15, 2005. NMOS 220 nm pitch Lecture 040 UDSM and BiCMOS Technologies (3/24/10) Page 040-4 CMOS Analog Circuit Design P.E. Allen - 2010 UDSM Metal and Interconnects Physical aspects: Layer Pitch (nm) Thickness (nm) Aspect Ratio Isolation 220 230- Polysilicon 220 90- Contacted Gate Pitch 220-- Metal 1 210 170 1.6 Metal 2 210 190 1.8 Metal 3 220 200 1.8 Metal 4 280 250 1.8 Metal 5 330 300 1.8 Metal 6 480 430 1.8 Metal 7 720 650 1.8 Metal 8 1080 975 1.8 Lecture 040 UDSM and BiCMOS Technologies (3/24/10) Page 040-5 CMOS Analog Circuit Design P.E. Allen - 2010 What are the Advantages of UDSM CMOS Technology? Digital Viewpoint: Improved I on / I off 70 Mbit SRAM chip: Reduced gate capacitance Higher drive current capability Reduced interconnect density Reduction of active power Analog Viewpoint: More levels of metal Higher f T Higher capacitance density Reduced junction capacitance per g m Lecture 040 UDSM and BiCMOS Technologies (3/24/10) Page 040-6 CMOS Analog Circuit Design P.E. Allen - 2010 What are the Disadvantages of UDSM CMOS Technology (for Analog)? Reduction in power supply resulting in reduced headroom Gate leakage currents Reduced small-signal intrinsic gains Increased nonlinearity (IIP3) Noise and matching??...
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Lect2UP040_(100324) - Lecture 040 UDSM and BiCMOS...

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