Lect2UP080_(100324) - Lecture 080 Latchup and ESD (3/24/10)...

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Lecture 080 – Latchup and ESD (3/24/10) Page 080-1 CMOS Analog Circuit Design © P.E. Allen - 2010 LECTURE 080 – LATCHUP AND ESD LECTURE ORGANIZATION Outline • Latchup • ESD • Summary CMOS Analog Circuit Design, 2 nd Edition Reference Pages 48-52 and new material Lecture 080 – Latchup and ESD (3/24/10) Page 080-2 CMOS Analog Circuit Design © P.E. Allen - 2010 LATCHUP What is Latchup? • Latchup is the creation of a low impedance path between the power supply rails. • Latchup is caused by the triggering of parasitic bipolar structures within an integrated circuit when applying a current or voltage stimulus on an input, output, or I/O pin or by an over-voltage on the power supply pin. • Temporary versus true latchup: A temporary or transient latchup occurs only while the pulse stimulus is connected to the integrated circuit and returns to normal levels once the stimulus is removed. A true latchup remains after the stimulus has been removed and requires a power supply shut down to remove the low impedance path between the power supply rails 070221-01 V DD E x c e s si v e C u r n t
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Lecture 080 – Latchup and ESD (3/24/10) Page 080-3 CMOS Analog Circuit Design © P.E. Allen - 2010 Latchup Testing The test for latchup defines how the designer must think about latchup. • For latchup prevention, you must consider where a current limited ( ± 100mA), 10ms pulse is going to go when applied to a pad when the voltage compliance of the pad is constrained to 50% above maximum power supply and to 2V below ground. (Higher temperatures, 85C°and 125°C, are more demanding, since V BE is lower.) 050727-06 V DD 100mA 10ms • Latchup is sensitive to layout and is most often solved at the physical layout level. Lecture 080 – Latchup and ESD (3/24/10) Page 080-4 CMOS Analog Circuit Design © P.E. Allen - 2010 How Does Latchup Occur? Latchup is the regenerative process that can occur in a pnpn structure (SCR-silicon controlled rectifier) formed by a parasitic npn and a parasitic pnp transistor. p p n n Anode Cathode Anode Cathode v PNPN i PNPN 1/Slope = Limiting Resistance Hold Current, I H Avalanche Breakdown V DD Triggering by increasing V DD Sustaining voltage, V S 050414-01 Hold Voltage, V H To avoid latchup v PNPN < V S v PNPN i PNPN Body diode (CMOS) Important concepts: • To avoid latchup, v PNPN ± V S • Once the pnpn structure has latched up, the large current required by the above i-v characteristics must be provided externally to sustain latchup • To remove latchup, the current must be reduced below the holding current
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Lecture 080 – Latchup and ESD (3/24/10) Page 080-5 CMOS Analog Circuit Design © P.E. Allen - 2010 Latchup Triggering Latchup of the SCR can be triggered by two different mechanisms. 1.) Allowing v PNPN to exceed the sustaining voltage, V S . 2.) Injection of current by a triggering device (gate triggered) Injector SCR 050414-03 SCR Anode Cathode pnp Gate npn Gate V DD Pad Gate Current Injector Pad Gate Current Note: The gates mentioned above are SCR junction gates, not MOSFET gates.
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This note was uploaded on 03/19/2012 for the course EE 3050 at Georgia Institute of Technology.

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Lect2UP080_(100324) - Lecture 080 Latchup and ESD (3/24/10)...

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