Lect2UP090_(100324) - Lecture 090 Large Signal MOSFET Model...

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Lecture 090 – Large Signal MOSFET Model (3/24/10) Page 090-1 CMOS Analog Circuit Design © P.E. Allen - 2010 LECTURE 090 – LARGE SIGNAL MOSFET MODEL LECTURE ORGANIZATION Outline • Introduction to modeling • Operation of the MOS transistor • Simple large signal model (SAH model) • Subthreshold model • Short channel, strong inversion model • Summary CMOS Analog Circuit Design, 2 nd Edition Reference Pages 73-78 and 97-99 Lecture 090 – Large Signal MOSFET Model (3/24/10) Page 090-2 CMOS Analog Circuit Design © P.E. Allen - 2010 INTRODUCTION TO MODELING Models Suitable for Understanding Analog Design The model required for analog design with CMOS technology is one that leads to understanding and insight as distinguished from accuracy. Technology Understanding and Usage Thinking Model Simple, ± 10% to ± 50% accuracy Design Decisions- "What can I change to accomplish . ...?" Computer Simulation Expectations "Ballpark" Extraction of Simple Model Parameters from Computer Models Comparison of simulation with expectations Refined and optimized design Updating Model Updating Technology Fig.3.0-02 This lecture is devoted to the simple model suitable for design not using simulation.
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Lecture 090 – Large Signal MOSFET Model (3/24/10) Page 090-3 CMOS Analog Circuit Design © P.E. Allen - 2010 Categorization of Electrical Models Time Dependence Time Independent Time Dependent Linearity Linear Small-signal, midband R in , A v , R out (.TF) Small-signal frequency response-poles and zeros (.AC) Nonlinear DC operating point i D = f ( v D , v G , v S , v B ) (.OP) Large-signal transient response - Slew rate (.TRAN) Based on the simulation capabilities of SPICE. Lecture 090 – Large Signal MOSFET Model (3/24/10) Page 090-4 CMOS Analog Circuit Design © P.E. Allen - 2010 OPERATION OF THE MOS TRANSISTOR Formation of the Channel for an Enhancement MOS Transistor Polysilicon p + p - substrate Fig.3.1-02 V B = 0 V G =V T V S = 0 V D = 0 p + p - substrate V B = 0 V G < V T V S = 0 V D = 0 Polysilicon p + p - substrate V B = 0 V G >V T V S = 0 V D = 0 Subthreshold ( V G < V T ) Threshold ( V G = V T ) Strong Threshold ( V G > V T ) Inverted Region Inverted Region Polysilicon n + n + n + n + n + n + Depletion Region
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Lecture 090 – Large Signal MOSFET Model (3/24/10) Page 090-5 CMOS Analog Circuit Design © P.E. Allen - 2010 Transconductance Characteristics of an Enhancement NMOSFET when V DS = 0.1V Polysilicon p + p - substrate Fig.3.1-03 V B = 0 V G = 2 V T V S = 0 V D = 0.1V p + p - substrate V B = 0 v G = V T V S = 0 V D = 0.1V Polysilicon p + p - substrate V B = 0 V G = 3 V T V S = 0 V D = 0.1V V GS V T : Inverted Region Inverted Region Polysilicon i D i D v GS V T 2 V T 3 V T 0 0 i D i D v GS V T 2 V T 3 V T 0 0 i D v GS V T 2 V T 3 V T 0 0 V GS =2 V T : V GS =3 V T : n + n + n + n + Depletion Region n + n + Lecture 090 – Large Signal MOSFET Model (3/24/10) Page 090-6 CMOS Analog Circuit Design © P.E. Allen - 2010 Output Characteristics of the Enhancement NMOS Transistor for V GS = 2 V T Fig.3.1-04 V B = 0 V G = 2 V T V S = 0 V D = 0.5V T v G =2 V T V D = 0V V B = 0 V S = 0 V D =V T V DS =0: i D v DS V T 0.5 V T 0 0 V DS =0.5 V T : V DS = V T : V G = 2 V T Polysilicon p + p - substrate V B = 0 V S = 0 Inverted Region i D i D v DS V T 0.5 V T 0 0 i D v DS V T 0.5 V T 0 0 Polysilicon p + p -
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Lect2UP090_(100324) - Lecture 090 Large Signal MOSFET Model...

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