Lect2UP100_(100324) - Lecture 100 MOS Capacitor Model and...

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Lecture 100 – MOS Capacitor Model and Large Signal Model Dependence (3/24/10) Page 100-1 CMOS Analog Circuit Design © P.E. Allen - 2010 LECTURE 100 – MOS CAPACITOR MODEL AND LARGE SIGNAL MODEL DEPENDENCE LECTURE ORGANIZATION Outline • MOSFET capacitor model • Dependence of the large signal model on process • Dependence of the large signal model on voltage • Dependence of the large signal model on temperature • Summary CMOS Analog Circuit Design, 2 nd Edition Reference Pages 79-86 Lecture 100 – MOS Capacitor Model and Large Signal Model Dependence (3/24/10) Page 100-2 CMOS Analog Circuit Design © P.E. Allen - 2010 MOSFET CAPACITOR MODEL Submicron Technology Physical perspective: SiO 2 Bulk Source Drain Gate C BS C BD C 4 C 1 C 2 C 3 Fig120-06 FOX FOX MOSFET capacitors consist of: Depletion capacitances Charge storage or parallel plate capacitances
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Lecture 100 – MOS Capacitor Model and Large Signal Model Dependence (3/24/10) Page 100-3 CMOS Analog Circuit Design © P.E. Allen - 2010 Deep Submicron Technology Physical perspective: MOSFET capacitors consist of: Depletion capacitances Charge storage or parallel plate capacitances Lecture 100 – MOS Capacitor Model and Large Signal Model Dependence (3/24/10) Page 100-4 CMOS Analog Circuit Design © P.E. Allen - 2010 MOSFET Depletion Capacitors Model: 1.) v BS ± FC · PB C BS = CJ · AS ² ³ ³ ´ µ · 1 - v BS PB MJ + CJSW · PS ² ³ ³ ´ µ · 1 - v BS MJSW , and 2.) v BS > FC · C BS = CJ · AS ² ´ µ · 1- FC 1+ MJ ² ³ ³ ´ µ · 1 - (1+ MJ ) FC + MJ V BS CJSW · ² ´ µ · 1 - FC 1+ MJSW ² ³ ³ ´ µ · 1 - (1+ MJSW ) FC + MJSW V BS SiO 2 Polysilicon gate Bulk A B C D E F G H Drain bottom = ABCD Drain sidewall = ABFE + BCGF + DCGH + ADHE Source Drain Fig. 120-07 FC·PB PB v BS C BS v BS FC·PB v BS FC·PB Fig. 120-08 where AS = area of the source PS = perimeter of the source CJSW = zero bias, bulk source sidewall capacitance MJSW = bulk-source sidewall grading coefficient For the bulk-drain depletion capacitance replace " S " by " D " in the above.
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Lecture 100 – MOS Capacitor Model and Large Signal Model Dependence (3/24/10) Page 100-5 CMOS Analog Circuit Design © P.E. Allen - 2010 SM Charge Storage (Parallel Plate) MOSFET Capacitances - C 1 , C 2 C 3 and C 4 Overlap capacitances: C 1 = C 3 = LD· W eff · C ox = CGSO or CGDO (LD ± 0.015 μ m for LDD structures) Channel capacitances: C 2 = gate-to-channel = C ox W ·( L -2LD) = C ox W · L C 4 = voltage dependent channel- bulk/substrate capacitance Bulk LD Mask W Oxide encroachment Actual L ( L eff ) Gate Mask L Source-gate overlap capacitance C GS ( C 1 ) Drain-gate overlap capacitance C GD ( C 3 ) Actual W ( W eff ) Fig. 120-09 Source Gate Drain Gate-Channel Capacitance ( C 2 ) FOX FOX Lecture 100 – MOS Capacitor Model and Large Signal Model Dependence (3/24/10) Page 100-6 CMOS Analog Circuit Design © P.E. Allen - 2010 SM Charge Storage (Parallel Plate) MOSFET Capacitances - C 5 View looking down the channel from source to drain Bulk Overlap Overlap Source/Drain Gate FOX FOX C 5 C 5 Fig120-10 C 5 = CGBO Capacitance values based on an oxide thickness of 140 Å or C ox =24.7 ± 10 -4 F/m 2 : Type
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Lect2UP100_(100324) - Lecture 100 MOS Capacitor Model and...

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