Lect2UP240_(100328)

Lect2UP240_(100328) - Lecture 240 Cascode Op Amps Page...

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Lecture 240 Cascode Op Amps (3/28/10) Page 240-1 CMOS Analog Circuit Design © P.E. Allen - 2010 LECTURE 240 – CASCODE OP AMPS LECTURE ORGANIZATION Outline • Lecture Organization • Single Stage Cascode Op Amps • Two Stage Cascode Op Amps • Summary CMOS Analog Circuit Design, 2 nd Edition Reference Pages 293-310 Lecture 240 Cascode Op Amps (3/28/10) Page 240-2 CMOS Analog Circuit Design © P.E. Allen - 2010 Cascode Op Amps Why cascode op amps? • Control of the frequency behavior • Can get more gain by increasing the output resistance of a stage • In the past section, PSRR of the two-stage op amp was insufficient for many applications • A two-stage op amp can become unstable for large load capacitors (if nulling resistor is not used) • The cascode op amp leads to wider ICMR and/or smaller power supply requirements Where Should the Cascode Technique be Used? First stage - Good noise performance Requires level translation to second stage Degrades the Miller compensation Second stage - Self compensating Increases the efficiency of the Miller compensation Increases PSRR
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Lecture 240 Cascode Op Amps (3/28/10) Page 240-3 CMOS Analog Circuit Design © P.E. Allen - 2010 SINGLE STAGE CASCODE OP AMPS Simple Single Stage Cascode Op Amp 060627-01 - + v in M1 M2 M3 M4 M5 v o 1 V DD V SS V NBias 1 + - V Bias 2 v in 2 - + MC2 MC1 MC4 MC3 - + v in M1 M2 M3 M4 M5 V DD V SS + - 2 v in 2 - + MC2 MC1 MC4 MC3 MB1 MB2 MB3 MB4 MB5 - + V Bias Implementation of the floating voltage V Bias which must equal 2 V ON + V T . V PBias 2 V NBias 1 V PBias 2 R out of the first stage is R I ± ( g mC 2 r dsC 2 r ds 2 )||( g mC 4 r dsC 4 r ds 4 ) Voltage gain = v o 1 v in = g m 1 R I [The gain is increased by approximately 0.5( g MC r dsC )] As a single stage op amp, the compensation capacitor becomes the load capacitor. Lecture 240 Cascode Op Amps (3/28/10) Page 240-4 CMOS Analog Circuit Design © P.E. Allen - 2010 Example 240-1 Single-Stage, Cascode Op Amp Performance Assume that all W / L ratios are 10 μ m/1 m, and that I DS 1 = I DS 2 = 50 A of single stage op amp. Find the voltage gain of this op amp and the value of C I if GB = 10 MHz. Use K N = 120 μ A/V 2 , K P ’ = 25 μ A/V 2 , V TN = 0.5V, V TP = -0.5V, ± N = 0.06V -1 and P = 0.08V -1 . Solution The device transconductances are g m 1 = g m 2 = g mI = 346.4 S g mC 1 = g mC 2 = 346.4 S g mC 3 = g mC 4 = 158.1 S. The output resistance of the NMOS and PMOS devices is 0.333 M ² and 0.25 M ² , respectively. ³ R I = 7.86 M ² A v (0) = 2,722 V/V. For a unity-gain bandwidth of 10 MHz, the value of C I is 5.51 pF. What happens if a 100pF capacitor is attached to this op amp? GB goes from 10MHz to 0.551MHz.
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Lecture 240 Cascode Op Amps (3/28/10) Page 240-5 CMOS Analog Circuit Design © P.E. Allen - 2010 060627-02 + - v IN v OUT M1 M2 M3 M4 M5 M6 M7 M8 M9 V DD V NB 1 -A -A -A + - v IN v OUT M1 M2 M3 M4 M5 M6 M7 M8 M9 V DD V NB 1 M10 V NB 1 V DD V DD V PB 1 M11 M12 M13 M14 M15 M16 Enhanced Gain, Single Stage, Cascode Op Amp From inspection, we can write the voltage gain as, A v = v OUT v IN = g m 1 R out where R out = ( Ar ds 6 g m 6 r ds 8 )|| ( Ar ds 2 g m 4 r ds 4 ) Since A ± g m r ds /2 the voltage gain would be equal to 100,000 to 500,000.
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This note was uploaded on 03/19/2012 for the course EE 3050 at Georgia Tech.

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Lect2UP240_(100328) - Lecture 240 Cascode Op Amps Page...

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