Lect2UP260_(100328) - Lecture 260 Buffered Op Amps...

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Lecture 260 – Buffered Op Amps (3/28/10) Page 260-1 CMOS Analog Circuit Design © P.E. Allen - 2010 LECTURE 260 – BUFFERED OP AMPS LECTURE ORGANIZATION Outline • Introduction • Open Loop Buffered Op Amps • Closed Loop Buffered Op Amps • Use of the BJT in Buffered Op Amps • Summary CMOS Analog Circuit Design, 2 nd Edition Reference Pages 352-368 Lecture 260 – Buffered Op Amps (3/28/10) Page 260-2 CMOS Analog Circuit Design © P.E. Allen - 2010 INTRODUCTION Buffered Op Amps What is a buffered op amp? Buffered op amps are op amps with the ability to drive a low output resistance and/or a large output capacitance. This requires: - An output resistance typically in the range of 10 ± ² R o ² 1000 ± - Ability to sink and source sufficient current ( C L · SR ) + - Op Amp Buffer R out Large R out Small v IN v OUT v OUT 070430-01 Types of buffered op amps: - Open loop using output amplifiers - Closed loop using negative shunt feedback to reduce the output resistance of the op amp
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Lecture 260 – Buffered Op Amps (3/28/10) Page 260-3 CMOS Analog Circuit Design © P.E. Allen - 2010 OPEN LOOP BUFFERED OP AMPS The Class A Source Follower as a Buffer • Simple • Small signal gain ± g m g m + g mbs + G L < 1 • Low efficiency R out = 1 g m + g mbs ± 500 to 1000 ± • Level shift from input to output • Maximum upper output voltage is limited • Broadbanded as the pole and zero due to the source follower are close so compensation is typically not a problem 060118-10 V NBias 1 V DD M1 M2 v IN v OUT Lecture 260 – Buffered Op Amps (3/28/10) Page 260-4 CMOS Analog Circuit Design © P.E. Allen - 2010 The Push-Pull Follower as a Buffer • Voltage loss from 2 cascaded followers A v ± ± ² ² ³ ´ µ µ g m 3 g m 3 + g mbs 3 ± ² ² ³ ´ µ µ g m 1 g m 1 + g mbs 1 + G L < 1 • Higher efficiency R out ± 0.5 g m + g mbs ± 250 to 500 · • Current in M1 and M2 determined by: V GS 4 + V SG 3 = V GS 1 + V SG 2 2 I 6 K n ' ( W 4 /L 4 ) + 2 I 5 K p ' ( W 3 /L 3 ) = 2 I 1 K n ' ( W 1 /L 1 ) 2 I 2 K p ' ( W 2 /L 2 ) Use the W/L ratios to define I 1 and I 2 from I 5 and I 6 • Maximum positive and negative output voltages are limited 060706-02 V NBias 1 V DD M1 M2 v IN v OUT V DD V DD M4 V DD V PBias 1 V DD M5 M3 M6 + - V SG 3 I 5 I 6 + - V SG 2 + - V GS 4 + - V GS 1 I 1 I 2
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Lecture 260 – Buffered Op Amps (3/28/10) Page 260-5 CMOS Analog Circuit Design © P.E. Allen - 2010 Two-Stage Op Amp with Follower - + v in M1 M2 M3 M4 M5 M6 M7 V NBias C c C L I 5 I 7 060706-03 V DD M8 M9 v out I 9 Power dissipation now becomes ( I 5 + I 7 + I 9 ) V DD Gain becomes, A v = ± ² ² ³ ´ µ µ g m 1 g ds 2 + g ds 4 ± ² ² ³ ´ µ µ g m 6 g ds 6 + g ds 7 ± ² ² ³ ´ µ µ g m 8 g m 8 + g mbs 8 + g ds 8 + g ds 9 Lecture 260 – Buffered Op Amps (3/28/10) Page 260-6 CMOS Analog Circuit Design © P.E. Allen - 2010 Source-Follower, Push-Pull Output Op Amp v out V DD V DD C c - + v in M1 M2 M3 V SS R 1 M5 M6 R 1 M7 M8 R 1 M13 M14 V SS V DD V SS M22 M21 I Bias M9 M10 M11 M12 M4 M17 M18 M15 M16 M19 M20 Fig. 7.1-1 C L Buffer - + V SG 18 - + V SG 21 - + V GS 19 - + V GS 22 I 17 I 20 R out ± 1 g m 21 + g m 22 ± 1000 ² , A v (0)=65dB ( I Bias =50 μ A), and GB = 60MHz for C L = 1pF Note the bias currents through M18 and M19 vary with the signal.
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This note was uploaded on 03/19/2012 for the course EE 3050 at Georgia Institute of Technology.

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Lect2UP260_(100328) - Lecture 260 Buffered Op Amps...

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