Lect2UP320(100328) - Lecture 320 Improved Open-Loop Comparators and Latches Page 320-1 LECTURE 320 IMPROVED OPEN-LOOP COMPARATORS AND LATCHES

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Lecture 320 – Improved Open-Loop Comparators and Latches (3/28/10) Page 320-1 CMOS Analog Circuit Design © P.E. Allen - 2010 LECTURE 320 – IMPROVED OPEN-LOOP COMPARATORS AND LATCHES LECTURE ORGANIZATION Outline • Autozeroing • Hysteresis • Simple Latches • Summary CMOS Analog Circuit Design, 2 nd Edition Reference Pages 464-483 Lecture 320 – Improved Open-Loop Comparators and Latches (3/28/10) Page 320-2 CMOS Analog Circuit Design © P.E. Allen - 2010 AUTOZEROING Principle of Autozeroing Use the comparator as an op amp to sample the dc input offset voltage and cancel the offset during operation. + - V OS V OS + - Ideal Comparator + - V OS Ideal Comparator C AZ V OS + - + - V OS Ideal Comparator C AZ v IN v OUT Model of Comparator. Autozero Cycle Comparison Cycle Fig. 8.4-1 Comments: The comparator must be stable in the unity-gain mode (self-compensating comparators are ideal, the two-stage comparator would require compensation to be switched in during the autozero cycle.) Complete offset cancellation is limited by charge injection
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Lecture 320 – Improved Open-Loop Comparators and Latches (3/28/10) Page 320-3 CMOS Analog Circuit Design © P.E. Allen - 2010 Differential Implementation of Autozeroed Comparators V OS + - + - V OS Ideal Comparator C AZ v IN - v OUT φ 1 φ 1 φ 1 φ 2 + - V OS v OUT = V OS V OS + - V OS Comparator during φ 1 phase Comparator during φ 2 phase Differential Autozeroed Comparator v OUT Fig. 8.4-2 v IN + φ 2 v IN + v IN - Lecture 320 – Improved Open-Loop Comparators and Latches (3/28/10) Page 320-4 CMOS Analog Circuit Design © P.E. Allen - 2010 Single-Ended Autozeroed Comparators Noninverting: φ 2 φ 2 φ 1 C AZ φ 1 φ 1 v OUT v IN Fig. 8.4-3 Inverting: φ 2 C AZ φ 1 φ 1 v OUT v IN Fig. 8.4-4 Comment on autozeroing: Need to be careful about noise that gets sampled onto the autozeroing capacitor and is present on the comparison phase of the process.
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Lecture 320 – Improved Open-Loop Comparators and Latches (3/28/10) Page 320-5 CMOS Analog Circuit Design © P.E. Allen - 2010 HYSTERESIS Influence of Input Noise on the Comparator Comparator without hysteresis: v in v out V OH V OL Comparator threshold t t Fig. 8.4-6A Comparator with hysteresis: v in v out V OH V OL t t V TRP + V TRP - Fig. 8.4-6B Lecture 320 – Improved Open-Loop Comparators and Latches (3/28/10) Page 320-6 CMOS Analog Circuit Design © P.E. Allen - 2010 Use of Hysteresis for Comparators in a Noisy Environment Transfer curve of a comparator with hysteresis: v OUT v IN V TRP + V TRP - V OH V OL Fig. 8.4-5 v OUT v IN V OH V OL 0 0 R 1 R 2 ( V OH - V OL ) V TRP + V TRP - Counterclockwise Bistable Clockwise Bistable Hysteresis is achieved by the use of positive feedback Externally Internally
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Lecture 320 – Improved Open-Loop Comparators and Latches (3/28/10) Page 320-7 CMOS Analog Circuit Design © P.E. Allen - 2010 Noninverting Comparator using External Positive Feedback Circuit: Upper Trip Point: Assume that v OUT = V OL , the upper trip point occurs when, 0 = ± ² ² ³ ´ µ µ R 1 R 1 + R 2 V OL + ± ² ² ³ ´ µ µ R 2 R 1 + R 2 V TRP + · V + = - R 1 R 2 V OL Lower Trip Point: Assume that v OUT = V OH
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Lect2UP320(100328) - Lecture 320 Improved Open-Loop Comparators and Latches Page 320-1 LECTURE 320 IMPROVED OPEN-LOOP COMPARATORS AND LATCHES

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