Lect2UP350_(100328)

Lect2UP350_(100328) - Lecture 350 Parallel DACs, Improved...

Info iconThis preview shows pages 1–4. Sign up to view the full content.

View Full Document Right Arrow Icon
Lecture 350 – Parallel DACs, Improved Resolution DACs and Serial DACs (3/28/10) Page 350-1 CMOS Analog Circuit Design © P.E. Allen - 2010 LECTURE 350 – PARALLEL DACS, IMPROVED DAC RESOLUTION AND SERIAL DACS LECTURE ORGANIZATION Outline • Voltage scaling DACs • Charge scaling DACs • Extending the resolution of parallel DACs • Serial DACs • Summary CMOS Analog Circuit Design, 2 nd Edition Reference Pages 626-652 Lecture 350 – Parallel DACs, Improved Resolution DACs and Serial DACs (3/28/10) Page 350-2 CMOS Analog Circuit Design © P.E. Allen - 2010 VOLTAGE SCALING DIGITAL-ANALOG CONVERTERS General Voltage Scaling Digital Analog Converter v OUT Voltage Scaling Network Digital Input Word V REF Decoder Logic V 1 V 2 V 3 V 2 N Fig. 10.2-6 Operation: Creates all possible values of the analog output then uses a decoding network to determine which voltage to select based on the digital input word.
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Lecture 350 – Parallel DACs, Improved Resolution DACs and Serial DACs (3/28/10) Page 350-3 CMOS Analog Circuit Design © P.E. Allen - 2010 3-Bit Voltage Scaling Digital-Analog Converter The voltage at any tap can be expressed as: v OUT = V REF 8 ( n ± 0.5) = V REF 16 (2 n ± 1) Attributes: • Guaranteed monotonic • Compatible with CMOS technology • Large area if N is large • Sensitive to parasitics • Requires a buffer • Large current can flow through the resistor string. b 2 b 1 b 0 b 2 b 1 b 0 V REF R /2 R /2 8 7 6 5 4 3 2 1 R R R R R R R v OUT 000 001 010 011 100 101 110 111 V REF 8 2V REF 8 3V REF 8 4V REF 8 5V REF 8 6V REF 8 7V REF 8 V REF 0 Digital Input Code v OUT (a.) (b.) Figure 10.2-7 - (a.) Implementation of a 3-bit voltage scaling DAC. (b.) Input-output characteristics of Fig. 10.2-7(a.) 11 16 V REF Input = 101 Lecture 350 – Parallel DACs, Improved Resolution DACs and Serial DACs (3/28/10) Page 350-4 CMOS Analog Circuit Design © P.E. Allen - 2010 Alternate Realization of the 3-Bit Voltage Scaling DAC b 2 b 1 b 0 V REF R /2 R /2 8 7 6 5 4 3 2 1 R R R R R R R v OUT 3-to-8 Decoder Fig. 10.2-8
Background image of page 2
Lecture 350 – Parallel DACs, Improved Resolution DACs and Serial DACs (3/28/10) Page 350-5 CMOS Analog Circuit Design © P.E. Allen - 2010 INL and DNL of the Voltage Scaling DAC Find an expression for the INL and DNL of the voltage scaling DAC using a worst-case approach. For an n -bit DAC, assume there are 2 n resistors between V REF and ground and that the resistors are numbered from 1 to 2 n beginning with the resistor connected to V REF and ending with the resistor connected to ground. Integral Nonlinearity The voltage at the i -th resistor from the top is, v i = (2 n - i ) R n - i ) R + iR V REF where there are i resistors above v i and 2 n -i below. For worst case, assume that i = 2 n -1 (midpoint). Define R max = R + ± R and R min = R - R . The worst case INL is INL = v 2 n -1 (actual) - v 2 n -1 (ideal) Therefore, INL = 2 n -1 ( R + R ) V 2 n ( R + R ) + 2 n ( R - R ) - V 2 = R 2 R V INL = 2 n 2 n ² ³ ³ ´ µ · R 2 R V =2 n ² ³ ³ ´ µ · R R ² ³ ³ ´ µ · V 2 n =2 n ² ³ ³ ´ µ · R R LSBs Differential Nonlinearity The worst case DNL is DNL = v step (act) - v step (ideal) Substituting the actual and ideal steps gives, = ( R ± R ) V 2 n R
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 4
This is the end of the preview. Sign up to access the rest of the document.

Page1 / 18

Lect2UP350_(100328) - Lecture 350 Parallel DACs, Improved...

This preview shows document pages 1 - 4. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online