Lect2UP380_(100329)

Lect2UP380_(100329) - Lecture 380 High Speed Nyquist ADCs...

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Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-1 CMOS Analog Circuit Design © P.E. Allen - 2010 LECTURE 380 – HIGH SPEED NYQUIST ADCS LECTURE ORGANIZATION Outline • Parallel/flash ADCs • Interpolating and averaging • Folding • High-speed, high-resolution ADCs • Time-interleaved ADCs CMOS Analog Circuit Design, 2 nd Edition Reference Pages 682-697 Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-2 CMOS Analog Circuit Design © P.E. Allen - 2010 PARALLEL/FLASH ADCs Parallel/Flash ADC Architecture 060928-01 Voltage Scaling Network creating all possible discrete analog voltages V REF V 1 V 2 V 3 V 4 V 2 N -1 Sample and Hold Circuit v in ( t ) v in * ( t ) 2 N -1 Compar ators d 1 d 2 d 3 d 4 d 2 N -1 2 N -1 to N Decoder b 1 b 2 b 3 b N Phase 1 Phase 2 One Clock Period, T Analog Input Digital Word Output • The notation, v in * ( t ), means the signal is sampled and held. • The sample and hold function can be incorporated into the comparators • The digital words designated as d i form a thermometer code
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Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-3 CMOS Analog Circuit Design © P.E. Allen - 2010 A 3-bit, parallel ADC General Comments: • Fast, in the first phase of the clock the analog input is sampled and applied to the comparators. In the second phase, the digital encoding network determines the correct output digital word. • Number of comparators required is 2 N -1 which can become large if N is large • The offset of the comparators must be less than ± V REF /2 N +1 • Errors occur as “bubbles” in the thermometer code and can be corrected with additional circuitry • Typical sampling frequencies can be as high as 1000MHz for 6-bits in sub-micron CMOS technology. 1 R + - 1 R + - 0 R + - 0 R + - 0 R + - 0 R + - 0 R + - V REF V in * = 0.7 V REF R 2 N -1 to N encoder Output Digital Word 101 0.875 V REF 0.750 V REF 0.625 V REF 0.500 V REF 0.375 V REF 0.250 V REF 0.125 V REF Fig.10.8-1 Lecture 380 – High Speed Nyquist ADCs (3/29/10) Page 380-4 CMOS Analog Circuit Design © P.E. Allen - 2010 Example 380-1 - Comparator Bandwidth Limitations on the Flash ADC The comparators of a 6-bit, flash ADC have a dominant pole at 10 4 radians/sec, a dc gain of 10 4 a slew rate of 10V/ μ s, and a binary output voltage of 1V and 0V. Assume that the conversion time is the time required for the comparator to go from its initial state to halfway to its final state. What is the maximum conversion rate of this ADC if V REF = 1V? Assume the resistor ladder is ideal. Solution: The output of the i -th comparator can be found by taking the inverse Laplace transform of, L -1 ± ² ² ³ ´ µ µ Vout( s ) = · ¸ ¸ ¹ º » » ¼ A o ( s /10 4 ) + 1 · · ¸ ¸ ¹ º » » ¼ V in *- V Ri s ½ v out ( t ) = A o (1 - e -10 4 t )( V in * - V ). The worst case occurs when V in *- V = 0.5 V LSB = V 7 = 1/128 ¾ 0.5V = 10 4 (1 - e -10 4 T )(1/128) ½ 64x10 -4 = 1- e -10 4 T or, e -10 4 T = 1 - 64x10 = 0.9936 ½ T = 10 ln(1.0064) = 0.6421 μ s ¾ Maximum conversion rate = 1 0.6421 μ s = 1.557x10 6 samples/second Checking the slew rate shows that it does not influence the maximum conversion rate.
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Lect2UP380_(100329) - Lecture 380 High Speed Nyquist ADCs...

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