74HC_HCT194_CNV_2

1 hc vm 50 vi gnd to vcc hct vm 13 v vi gnd

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Unformatted text preview: to clock (CP) removal time. The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.10 Waveforms showing the set-up and hold times from the mode control inputs (Sn) to the clock input (CP). PACKAGE OUTLINES Fig.9 Waveforms showing the set-up and hold times from the data inputs (Dn, DSR and DSL) to the clock (CP). See “74HC/HCT/HCU/HCMOS Logic Package Outlines”. December 1990 10...
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This note was uploaded on 03/21/2012 for the course COMP EE357 taught by Professor Vanloon during the Fall '10 term at Mohawk College.

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