74HC_HCT194_CNV_2

145 29 25 140 28 24 75 15 13 100 20 17 100 20 17 75

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Unformatted text preview: 70 14 12 80 16 12 70 14 12 0 0 0 0 0 0 0 0 0 17 6 5 17 6 5 17 6 5 17 6 5 22 8 6 19 7 6 −14 −5 −4 −11 −4 −3 −17 −6 −5 31 93 111 max. 145 29 25 140 28 24 75 15 13 100 20 17 100 20 17 75 15 13 90 18 15 100 20 17 90 18 15 0 0 0 0 0 0 0 0 0 4.8 24 28 −40 to +85 min. max. 180 36 31 175 35 30 95 19 16 120 24 20 120 24 20 90 18 15 105 21 18 120 24 20 105 21 18 0 0 0 0 0 0 0 0 0 4.0 20 24 −40 to +125 min. max. 220 44 38 210 42 36 110 22 19 ns UNIT 74HC/HCT194 TEST CONDITIONS VCC WAVEFORMS (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Fig.7 Fig.9 Fig.7 tPHL ns Fig.8 tTHL/ tTLH ns Fig.7 tW clock pulse width HIGH or LOW master reset pulse width; LOW removal time MR to CP set-up time Dn to CP set-up time S0, S1 to CP set-up time DSR, DSL to CP hold time Dn to CP hold time S0, S1 to CP hold time DSR, DSL to CP ns Fig.7 tW ns Fig.8 trem ns Fig.8 tsu ns Fig.9 tsu ns Fig.10 tsu ns th ns th ns Fig.10 th ns fmax maximum clock pulse 6.0 frequency 30 35 MHz December 1990 7 Philips Semiconductors Product specification 4-bit bidirectional universal shif...
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This note was uploaded on 03/21/2012 for the course COMP EE357 taught by Professor Vanloon during the Fall '10 term at Mohawk College.

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