74HC_HCT194_CNV_2

74HC_HCT194_CNV_2 - INTEGRATED CIRCUITS DATA SHEET For a...

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Unformatted text preview: INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT194 4-bit bidirectional universal shift register Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification 4-bit bidirectional universal shift register FEATURES • Shift-left and shift-right capability • Synchronous parallel and serial data transfer • Easily expanded for both serial and parallel operation • Asynchronous master reset • Hold (“do nothing”) mode • Output capability: standard • ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT194 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The functional characteristics of the 74HC/HCT194 4-bit bidirectional universal shift registers are indicated in the logic diagram and function table. The registers are fully synchronous. The “194” design has special features which increase the range of application. The synchronous operation of the device is determined by the mode select inputs (S0, S1). As shown in the mode select table, data can be entered QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns 74HC/HCT194 and shifted from left to right (Q0 → Q1 → Q2, etc.) or, right to left (Q3 → Q2 → Q1, etc.) or parallel data can be entered, loading all 4 bits of the register simultaneously. When both S0 and S1 are LOW, existing data is retained in a hold (“do nothing”) mode. The first and last stages provide D-type serial data inputs (DSR, DSL) to allow multistage shift right or shift left data transfers without interfering with parallel load operation. Mode select and data inputs are edge-triggered, responding only to the LOW-to-HIGH transition of the clock (CP). Therefore, the only timing restriction is that the mode control and selected data inputs must be stable one set-up time prior to the positive transition of the clock pulse. The four parallel data inputs (D0 to D3) are D-type inputs. Data appearing on the D0 to D3 inputs, when S0 and S1 are HIGH, is transferred to the Q0 to Q3 outputs respectively, following the next LOW-to-HIGH transition of the clock. When LOW, the asynchronous master reset (MR) overrides all other input conditions and forces the Q outputs LOW. The “194” is similar in operation to the “195” universal shift register, with added features of shift-left without external connections and hold (“do nothing”) modes of operation. TYPICAL SYMBOL tPHL/ tPLH tPHL fmax CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ = (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC; for HCT the condition is VI = GND to VCC − 1.5 V December 1990 2 PARAMETER propagation delay CP to Qn MR to Qn maximum clock frequency input capacitance power dissipation capacitance per package notes 1 and 2 CONDITIONS HC CL = 15 pF; VCC = 5 V 14 11 102 3.5 40 15 15 77 3.5 40 ns ns MHz pF pF HCT UNIT Philips Semiconductors Product specification 4-bit bidirectional universal shift register ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”. PIN DESCRIPTION PIN NO. 1 2 3, 4, 5, 6 7 8 9, 10 11 15, 14, 13, 12 16 SYMBOL MR DSR D0 to D3 DSL GND S0, S1 CP Q0 to Q3 VCC NAME AND FUNCTION asynchronous master reset input (active LOW) serial data input (shift right) parallel data inputs serial data input (shift left) ground (0 V) mode control inputs clock input (LOW-to-HIGH edge-triggered) parallel outputs positive supply voltage 74HC/HCT194 Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol. December 1990 3 Philips Semiconductors Product specification 4-bit bidirectional universal shift register 74HC/HCT194 Fig.4 Functional diagram. FUNCTION TABLE INPUTS OPERATING MODES CP reset (clear) hold (“do nothing”) shift left shift right parallel load Notes 1. H h L I q,d X ↑ = HIGH voltage level = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition = LOW voltage level = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition = lower case letters indicate the state of the referenced input (or output) one set-up time prior to the LOW-to-HIGH CP transition = don’t care = LOW-to-HIGH CP transition X X ↑ ↑ ↑ ↑ ↑ MR L H H H H H H S1 X I h h I I h S0 X I I I h h h DSR X X X X I h X DSL X X I h X X X Dn X X X X X X dn Q0 L q0 q1 q1 L H d0 Q1 L q1 q2 q2 q0 q0 d1 Q2 L q2 q3 q3 q1 q1 d2 Q3 L q3 L H q2 q2 d3 OUTPUTS December 1990 4 Philips Semiconductors Product specification 4-bit bidirectional universal shift register 74HC/HCT194 Fig.5 Logic diagram. Fig.6 Typical clear, clear-load, shift-right, shift-left, inhibit and clear timing sequences. December 1990 5 Philips Semiconductors Product specification 4-bit bidirectional universal shift register DC CHARACTERISTICS FOR 74HC For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: MSI 74HC/HCT194 December 1990 6 Philips Semiconductors Product specification 4-bit bidirectional universal shift register AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) 74HC SYMBOL PARAMETER +25 min. typ. tPHL/ tPLH propagation delay CP to Qn propagation delay MR to Qn output transition time 47 17 14 39 14 11 19 7 6 80 16 14 80 16 14 60 12 10 70 14 12 80 16 12 70 14 12 0 0 0 0 0 0 0 0 0 17 6 5 17 6 5 17 6 5 17 6 5 22 8 6 19 7 6 −14 −5 −4 −11 −4 −3 −17 −6 −5 31 93 111 max. 145 29 25 140 28 24 75 15 13 100 20 17 100 20 17 75 15 13 90 18 15 100 20 17 90 18 15 0 0 0 0 0 0 0 0 0 4.8 24 28 −40 to +85 min. max. 180 36 31 175 35 30 95 19 16 120 24 20 120 24 20 90 18 15 105 21 18 120 24 20 105 21 18 0 0 0 0 0 0 0 0 0 4.0 20 24 −40 to +125 min. max. 220 44 38 210 42 36 110 22 19 ns UNIT 74HC/HCT194 TEST CONDITIONS VCC WAVEFORMS (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Fig.7 Fig.9 Fig.7 tPHL ns Fig.8 tTHL/ tTLH ns Fig.7 tW clock pulse width HIGH or LOW master reset pulse width; LOW removal time MR to CP set-up time Dn to CP set-up time S0, S1 to CP set-up time DSR, DSL to CP hold time Dn to CP hold time S0, S1 to CP hold time DSR, DSL to CP ns Fig.7 tW ns Fig.8 trem ns Fig.8 tsu ns Fig.9 tsu ns Fig.10 tsu ns th ns th ns Fig.10 th ns fmax maximum clock pulse 6.0 frequency 30 35 MHz December 1990 7 Philips Semiconductors Product specification 4-bit bidirectional universal shift register DC CHARACTERISTICS FOR 74HCT For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: MSI Note to HCT types 74HC/HCT194 The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications. To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT Dn DSR, DSL CP MR Sn UNIT LOAD COEFFICIENT 0.15 0.15 0.50 0.45 0.90 December 1990 8 Philips Semiconductors Product specification 4-bit bidirectional universal shift register AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) 74HCT SYMBOL PARAMETER min. tPHL/ tPLH tPHL tTHL/ tTLH tW tW trem tsu tsu tsu th th th fmax propagation delay CP to Qn propagation delay MR to Qn output transition time clock pulse width HIGH or LOW master reset pulse width; LOW removal time MR to CP set-up time Dn to CP set-up time S0, S1 to CP set-up time DSR, DSL to CP hold time Dn to CP hold time S0, S1 to CP hold time DSR, DSL to CP 16 16 12 14 20 14 0 0 0 −7 −5 −7 70 +25 typ. 18 18 7 7 7 6 7 10 −40 to +85 max. min. 32 32 15 20 20 15 18 25 18 0 0 0 24 max. 40 40 19 24 24 18 21 30 21 0 0 0 20 −40 to +125 min. max. 48 48 22 ns ns ns ns ns ns ns ns ns ns ns ns MHz UNIT 74HC/HCT194 TEST CONDITIONS VCC (V) 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 WAVEFORMS Fig.7 Fig.8 Fig.7 Fig.7 Fig.8 Fig.8 Fig.9 Fig.10 Fig.9 Fig.9 Fig.10 Fig.9 Fig.7 maximum clock pulse 30 frequency December 1990 9 Philips Semiconductors Product specification 4-bit bidirectional universal shift register AC WAVEFORMS 74HC/HCT194 (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.7 Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock pulse width, the output transition times and the maximum clock frequency. Fig.8 Waveforms showing the master reset (MR) pulse width, the master reset to output (Qn) propagation delays and the master reset to clock (CP) removal time. The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.10 Waveforms showing the set-up and hold times from the mode control inputs (Sn) to the clock input (CP). PACKAGE OUTLINES Fig.9 Waveforms showing the set-up and hold times from the data inputs (Dn, DSR and DSL) to the clock (CP). See “74HC/HCT/HCU/HCMOS Logic Package Outlines”. December 1990 10 ...
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This note was uploaded on 03/21/2012 for the course COMP EE357 taught by Professor Vanloon during the Fall '10 term at Mohawk College.

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