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Unformatted text preview: -up time prior to the positive transition of the clock pulse. The four parallel data inputs (D0 to D3) are D-type inputs. Data appearing on the D0 to D3 inputs, when S0 and S1 are HIGH, is transferred to the Q0 to Q3 outputs respectively, following the next LOW-to-HIGH transition of the clock. When LOW, the asynchronous master reset (MR) overrides all other input conditions and forces the Q outputs LOW. The “194” is similar in operation to the “195” universal shift register, with added features of shift-left without external connections and hold (“do nothing”) modes of operation. TYPICAL SYMBOL tPHL/ tPLH tPHL fmax CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ = (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC; for HCT the condition is VI = GND to VCC − 1.5 V December 1990 2 PARAMETER propagation delay CP to Qn MR to Qn maximum clock frequency input capacitance pow...
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This note was uploaded on 03/21/2012 for the course COMP EE357 taught by Professor Vanloon during the Fall '10 term at Mohawk College.
- Fall '10