74HC_HCT194_CNV_2

Min 32 32 15 20 20 15 18 25 18 0 0 0 24 max 40 40 19

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Unformatted text preview: CP hold time S0, S1 to CP hold time DSR, DSL to CP 16 16 12 14 20 14 0 0 0 −7 −5 −7 70 +25 typ. 18 18 7 7 7 6 7 10 −40 to +85 max. min. 32 32 15 20 20 15 18 25 18 0 0 0 24 max. 40 40 19 24 24 18 21 30 21 0 0 0 20 −40 to +125 min. max. 48 48 22 ns ns ns ns ns ns ns ns ns ns ns ns MHz UNIT 74HC/HCT194 TEST CONDITIONS VCC (V) 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 WAVEFORMS Fig.7 Fig.8 Fig.7 Fig.7 Fig.8 Fig.8 Fig.9 Fig.10 Fig.9 Fig.9 Fig.10 Fig.9 Fig.7 maximum clock pulse 30 frequency December 1990 9 Philips Semiconductors Product specification 4-bit bidirectional universal shift register AC WAVEFORMS 74HC/HCT194 (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.7 Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock pulse width, the output transition times and the maximum clock frequency. Fig.8 Waveforms showing the master reset (MR) pulse width, the master reset to output (Qn) propagation delays and the master reset...
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This note was uploaded on 03/21/2012 for the course COMP EE357 taught by Professor Vanloon during the Fall '10 term at Mohawk College.

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