cd74hc93 - CD74HC93, CD74HCT93 Data sheet acquired from...

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1 Data sheet acquired from Harris Semiconductor SCHS138C Features • Can Be Configured to Divide By 2, 8, and 16 • Asynchronous Master Reset • Fanout (Over Temperature Range) - Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wide Operating Temperature Range . . . -55 o C to 125 o C • Balanced Propagation Delay and Transition Times • Significant Power Reduction Compared to LSTTL Logic ICs • HC Types - 2V to 6V Operation - High Noise Immunity: N IL = 30%, N IH = 30% of V CC at V CC = 5V • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, V IL = 0.8V (Max), V IH = 2V (Min) - CMOS Input Compatibility, I l 1 µ A at V OL , V OH Pinout CD74HC93 (PDIP, SOIC) CD74HCT93 (PDIP) TOP VIEW Description The CD74HC93 and CD74HCT93 are high-speed silicon-gate CMOS devices and are pin-compatible with low power Schottky TTL (LSTTL). These 4-bit binary ripple counters consist of four master-slave flip-flops internally connected to provide a divide-by-two section and a divide- by-eight section. Each section has a separate clock input ( CP0 and CP1) to initiate state changes of the counter on the HIGH to LOW clock transition. State changes of the Q n outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and should not be used for clocks or strobes. A gated AND asynchronous master reset (MR1 and MR2 is provided which overrides both clocks and resets (clears) all flip-flops. Because the output from the divide by two section is not internally connected to the succeeding stages, the device may be operated in various counting modes. In a 4-bit ripple counter the output Q 0 must be connected externally to input CP1. The input count pulses are applied to clock input CP0. Simultaneous frequency divisions of 2, 4, 8, and 16 are performed at the Q 0 ,Q 1 2 , and Q 3 outputs as shown in the function table. As a 3-bit ripple counter the input count pulses are applied to input CP1. Simultaneous frequency divisions of 2, 4, and 8 are available at the Q 1 2 3 outputs. Independent use of the first flip- flop is available if the reset function coincides with the reset of the 3-bit ripple-through counter. CP1 MR1 MR2 NC V CC NC NC CPO NC Q 0 Q 3 GND Q 1 Q 2 1 2 3 4 5 6 7 14 13 12 11 10 9 8 Ordering Information PART NUMBER TEMP. RANGE ( o C) PACKAGE CD74HC93E -55 to 125 14 Ld PDIP CD74HC93M -55 to 125 14 Ld SOIC CD74HC93MT -55 to 125 14 Ld SOIC CD74HC93M96 -55 to 125 14 Ld SOIC CD74HCT93E -55 to 125 14 Ld PDIP NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of 250. August 1997 - Revised September 2003 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, Texas Instruments Incorporated CD74HC93, CD74HCT93 High-Speed CMOS Logic 4-Bit Binary Ripple Counter [ /Title (CD74 HC93, CD74 HCT93 ) /Sub- ject (High Speed CMOS Logic 4-Bit Binary Ripple Counte r)
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2 TRUTH TABLE COUNT OUTPUTS Q 0 Q 1 Q 2 Q 3 0LLLL 1HLLL 2LHLL 3HHLL 4LLHL 5HLHL 6LHHL 7HHHL 8LLLH 9HLLH 1 0LHLH 11 H H L H 12 L L H H 13 H
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This note was uploaded on 03/21/2012 for the course COMP EE357 taught by Professor Vanloon during the Fall '10 term at Mohawk College.

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cd74hc93 - CD74HC93, CD74HCT93 Data sheet acquired from...

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