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Unformatted text preview: ELSIF (ClockEVENT AND Clock = 1) THEN State <= nextState; END IF; END PROCESS ; PROCESS (state, InBit, BufFull) -- conditional and uncond. Outputs, next state BEGIN -- All outputs are default to '0' CountEN <= '0'; RegLD <= '0'; OutFlag <= '0'; CASE state IS WHEN A => CountEN <= '1'; RegLD <= '1'; IF InBit = '0' THEN nextState <= B ; ELSE nextState <= C ; END IF ; WHEN B => nextState <= A; WHEN C => RegLD <= '1'; IF BufFull = '1' THEN CountEN <= '1'; nextState <= D; ELSE nextState <= C; END IF ; WHEN D => OutFlag <= '1'; nextState <= A; WHEN OTHERS => nextState <= A; END CASE ; END PROCESS ; END ASMArch ;...
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This note was uploaded on 03/27/2012 for the course EEL 4930 taught by Professor Staff during the Spring '08 term at University of Florida.
- Spring '08