Lab2a - Lab 2(a): VHDL Finite State Machine and Datapath...

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1 Lab 2(a): VHDL – Finite State Machine and Datapath EEL 4930/5934 – Spring 2012 Objective: The objective of Lab 2(a) is to design and simulate a circuit in VHDL that calculates Fibonacci numbers. Fibonacci Calculator Introduction: For this part of the lab, you will be implementing a circuit in VHDL that calculates Fibonacci numbers. Here is the pseudocode that describes the behavior of the circuit: Input: n (specifies that the Fibonacci number to be calculated) Output: result (the nth Fibonacci number) i = 3; x = 1; y = 1; while (i <= n) { temp = x+y; x = y; y = temp; i ++; } result = y; Modeling a controller and datapath (FSM+D) In this part of the lab, you will implement a controller and datapath in VHDL to implement the functionality of the code shown above. A block diagram of the circuit is shown below:
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2 The circuit has 4 inputs: go , n (generic width) , and clock/reset (not shown). There are also 2 outputs: done and result (generic width). The circuit should initially wait until
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Lab2a - Lab 2(a): VHDL Finite State Machine and Datapath...

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