Lab4Spring2012 - Lab 4 Simple Pipelined Datapath EEL...

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Lab 4: Simple Pipelined Datapath EEL 4930/5934 – Spring 2012 1 Introduction: In this lab, you will be implementing a circuit with a pipelined datapath. The circuit will utilize one blockRAM (BRAM) to continually feed four 8-bit inputs into the datapath every cycle, and one BRAM to store an output each cycle. In software, you will initially transfer data from the microprocessor into the input BRAM, specify the array size, start the circuit using a “go” signal, and then wait for completion, at which point the software will read data from the output BRAM and output it to the screen. The pseudo-code for the algorithm that you will be implementing on the FPGA is shown below. Obviously your actual code will be in VHDL and will look nothing like this. It is simply intended to help you understand the functionality. for(i=0,j=0; j < OUTPUT_SIZE; i += 4, j++) { a[j] = b[i]*b[i+1] + b[i+2]*b[i+3]; } Note that there is no overlap of inputs between iterations because i is incremented by 4 each iteration. For example: a[0] = b[0]*b[1] + b[2]*b[3], a[1] = b[4]*b[5] + b[6]*b[7], etc. Pipelined Datapath The following pipelined datapath will be specified in structural VHDL: As shown, the pipeline takes four 8-bit inputs. In the first stage of the pipeline, each pair of inputs is multiplied to produce two 16-bit numbers. In the next stage, the products are added. The rectangular boxes are registers that have an enable signal that can stall the pipeline when not asserted. For this lab, the enable signal is not necessary because the pipeline won't ever need to stall. However, it is recommended that you use one since you may need it for future projects. Create this datapath using a structural VHDL description that instantiates registers, multipliers, and an adder. It is highly recommended that the generate statements and arrays to be used here to make the code more concise. NOTE: The datapath takes four 8-bit inputs and produces one 17-bit output. However, the provided blockRAM code (see dual_port_ram entity ) uses 32-bit inputs/outputs. Therefore, to get four inputs to the datapath each cycle, you must divide each 32-bit input into four 8-bit inputs. Similarly, you must concatenate an appropriate number of 0's onto each output before writing it to the output BRAM.
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Lab 4: Simple Pipelined Datapath EEL 4930/5934 – Spring 2012 2 Overall Circuit The overall circuit (VHDL and DIMEtalk) is shown below: pipeline_h101 is the top-level VHDL entity which must be imported into DIMEtalk. Memory Map
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This note was uploaded on 03/27/2012 for the course EEL 4930 taught by Professor Staff during the Spring '08 term at University of Florida.

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Lab4Spring2012 - Lab 4 Simple Pipelined Datapath EEL...

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