Lab5Spring2012 - Lab 5: Clock Domain Crossing EEL 4930/5934...

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Lab 5: Clock Domain Crossing EEL 4930/5934 – Spring 2012 1 Introduction: In this lab, you will learn how to properly communicate across clock domains. If not handled correctly, signals that cross clock domains can become metastable, which if propagated through your circuit will likely cause errors. In this lab, you will learn how to create FIFO synchronizers that enable signals to be stabilized before being used in the destination domain. In Part 1, FIFOs are used to synchronize between on-chip BRAMs and the datapath running in a different clock domain. In Part 2, FIFOs are used to synchronize between an off-chip (on-board) SRAM and the datapath. Part 1: FIFO to synchronize BRAMs and datapath Shown in Figure 1 is a block diagram design of the circuit to be implemented. In this part of the lab, the FIFOs are used to synchronize between on-chip BRAMs and the datapath running in a different clock domain. As described in class, to synchronize signals running in different clock domains, a FIFO provides a clock for writing and a different one for reading. The input address generator (BRAM_In AddrGen) produces an address (i.e, increment address counter) anytime the input FIFO is not full. For Part 1 of this lab, because there is one cycle of latency for a memory read (from BRAM_In), the address generator must stop when the ALMOST_FULL flag of FIFO is true (indicating only one word of the FIFO is left), as shown in Figure 1. This flag is used to insure that there is enough room in the FIFO to store an outstanding memory read request. For memories with different delays (e.g., external memories like SRAM), you must use a FIFO with a programmable FULL flag (i.e., user can define a constant other than 1 as in the ALMOST_FULL flag) that leaves enough room for all outstanding memory read requests. One advantage of using FIFOs is simplified control. In fact, for this design, an explicit controller is not
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Lab5Spring2012 - Lab 5: Clock Domain Crossing EEL 4930/5934...

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