EEL 4930/5934 Reconfigurable Computing
Midterm Exam – Spring Semester 2010
Name ___________________________________
1
1. Systolic Architecture
(
a) Given the following algorithm in pseudo-code, draw a datapath that is fully-pipelined and
with the maximum loop-unrolling.
for (i=1; i < 10000; i++) {
z[i] = avg(a[i-1] + a[i] + a[i+1]);
}
Assume the memory bandwidth is 64 bits and data items are 16 bits.
(
b) Calculate the speedup of the above circuit (assuming the FPGA clock rate of 200 MHz)
as compared to the corresponding software executing on a microprocessor (assume 15
instructions for each iteration, a CPI of 2, and clock frequency of 3 GHz).
(
c) Using the same assumptions as above except the memory bandwidth is increased to 128
bits, calculate the speedup of the resulting circuit (using the maximum amount of loop
unrolling) as compared to the corresponding software executing on a microprocessor.
18 pts
.

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