MidtermSpring2010Solution

MidtermSpring2010Solution - EEL 4930/5934 Reconfigurable...

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Unformatted text preview: EEL 4930/5934 Reconfigurable Computing Midterm Exam - Spring Semester 2010 Name _ 1. Systolic Architecture (a) Given the following algorithm in pseudo—code, draw a datapath that is fully—pipelined and - with the maximum loop-unrolling. for (i=1; i < 10000; i++) { z[i] = avg(al£.-1] + a[i] + a[i+1]); } ./5 Assume the memory bandwidth is 64 bits and data items are 16 bits. 4/14] 40'] am] 4502] . l Jj l m L“ l: T+/ - /— , \ WIT—71.2 10g, 4;?3 £7 £3 1’54 4:43 4¢éf 33 5% vii—3. Ari/é 4;» 4; 44 Q7 35’ g6 , , l ; pi-u i l r""""l 2H] 222:!va (b) Calculate the speedup of the above circuit (assuming the FPGA clock rate of 200 MHz) as compared to the corresponding software executing on a microprocessor (assume 15 instructions for each iteration, a CPI of 2, and clock frequency of 3 GHz). MW ¢¢W #4 /fi' 442 #44: 5+ €27.7gtflyf 2 ,» f??? a’é/{éfli W 53%? *l‘/§" \: $4x (c) Using the same assumptions as above except the memory bandwidth is increased to 128 bits, calculate the speedup of the resulting circuit (using the maximum amount of loop unrolling) as compared to the corresponding software executing on a microprocessor. Ffléfl m MW /.2 2,943.: w M; =7 éfimw (km/p (7WZ—é2557é/56VQ /é Wage/r0 // ; ¢W€~£¢X§¥£ -://J-¢7$ 2 /é7/4¢/5’ ' / X EEL 4930/5934 Reconfigurable Computing Midterm Exam — Spring Semester 2010 Name 2. Smart Buffer This problem makes use of the algorithm (pseudo code) and the systolic architecture of Problem 1, but with the following design and assumptions. Input addr ' B RAM Assumptions: 6 5 - Memory bandwidth is 32 bits. 4 151 761p171p18 0 Data item are 8bits. 3 p11 :p12 : 13 : 14 2 p7 P8 5 9 U370 However, we want the bandwidth into the 5 N I 4 i p5 E p6 datapath to be 48 bits. For that reason, a smart XX : XX 1 p14 2 bufferis used. This smart buffer is similar to the one explained in class. The difference is that this smart buffer only uses 6 bytes (instead of the 8—byte one in class). (a) Specify the contents of the smart buffer after each of the following clock cycle. X )( /r / / after clock cyclet after clock cycle 2 after clock cycle 3 ,’ 7‘ /’ 2// f 2/3 _/- v mclock cycle4 (b) Briefly describe what happens at each clock cyCIe. Keep the algorithm as uniform as possible. cycie1: ' aamméfiawww “WZ Cycle 2: u \ ll 1/ l/ 5 M, y! u' l/ W I .- 0 I / I I M EEL 4930/5934 Reconfigurable Computing Midterm Exam — Spring Semester 2010 Name 3. Memo Ma and Glue Lo ic Code Given below is a block diagram of a DlMEtalk memory map node and how it is interfaced to the Glue Logic similar to that of Lab 3. (To/From (TO/From v reset] —————L——J—>addr31‘é0n go TopLevel g PCIX bUS) dt_clk Memory ————————> Glue d VHDL data_in Map node Tm, Logic one module) data_out mfi—J— result[31..0] dt clk——> Given below is the part of the C program relevant to the writing of the “go” signal and the reading of the “done” and “result” signals. Note for both FPGA_read and FPGA_write, the parameter list is (data, wordcount, address, node, timeout). go = 1; done = O; FPGA_write(&go,1,2,MemMap,1000); while(done != 1) { FPGA_read(&done,1,3, MemMap,lOOO); } FPGA_read(&result,1,5,MemMap,1000) (a) Complete the following VHDL code (a part of the Glue Logic module) that handles the “go” , “done”, and “result” signals. Assume that the PORT statement has been defined and use the signal names shown in the block diagram above. ) ARCHITECTURE Behavioral OF GlueLogic IS SIGNAL 2:82;“ ) :EgN/MAM Eva/V7 AW) fl,dM = ‘/ y 7450 IF fl“ ‘/ ’ 75/5” _ IF MM:— ’/ ’ ffla/ “m fjfla. If M = X ’vpflmwaz ” 745W .. w: MflIflJ ,1 E 04‘; KM? /F 3 gas/F. 4/617 =3 ’ 7%!” 5/5! W /5 Wfléfl X Wpran ” —— W/%2c< . {4929422 wag - "9% m; 3/’ . W/%// X "aw/wag“ ~ ’MW 5.27 4; W,’ Wflg/ flffl%! => /’ END IF' ’ . 5“? {/55 ' END PROCESSgW A” 2 3 END Behavioriéiép //53 EEL 4930/5934 Reconfigurable Computing Midterm Exam — Spring Semester 2010 Name 4. Glue Logic Circuit Diagram - Based on the glue logic code you gave in Problem 3, draw the circuit diagram that corresponds to the VHDL code. You can use components such as flipflops, registers, mux’s, comparators, and any gates. Flip-flop 32-bit register 32-bit comparator D[31..0] Z[31..0] AddrBLm Z EN True or 1 I > I Value [31..0] False , r ".\\~\.n GlueLOg'ic component """\\ i l i l addr[31..0] en wen data_in[31..0] data_out[31..0] ——> dtclk (assume connected to all necessary components) 3 i l . 3 l i Z i i l l l l l EEL 4930/5934 Reconfigurable Computing Midterm Exam — Spring Semester 2010 Name 5. Analysis of VHDL code . 2 - Sometimes to debug the VHDL code of a controller, it is necessary to reverse-engineer the code to determine its timing behavior and the corresponding ASM chart. Given below is the VHDL code below of a controller. On the next page, (a) determine its timing behavior and (b) I construct the corresponding ASM chart. ENTITY Contr IS PORT ( Clock, Resetn, Go : IN STD_LOGIC ; EnY, EnZ : OUT STD_LOGIC ) ; END Contr; ARCHITECTURE ASMArch OFContr IS SIGNAL state : STD__LOGIC_VECTOR (1 DOWNTO 0) ; BEGIN PROCESS (Resetn, Clock) BEGIN IF Resetn = '0' THEN state <= “10"; ELSIF (CIOCk’EVENT AND Clock = ‘1’) THEN 4/ E i E . I i . I E CASE state IS WHEN “00" => IF G0 = ‘0’ THEN state <= “00”; ELSE state <= “10"; END IF; WHEN “01” => state <= “10"; WHEN “10” => 1 IF G0 = ‘0’ THEN state <= “00"; ELSE state <= “01”; END IF; WHEN OTHERS => state <= “10"; END CASE ; END IF ; END PROCESS ; PROCESS (state, Go) BEGIN EnY <= '0’; EnZ <= ‘0’; CASE state IS WHEN “00" => WHEN “01"=> EnY <= ‘1’; 1 WHEN “10" => 1 EnZ <= ‘1 ’; IF G0 = ‘0’ THEN EnY <= ‘1’; it END IF; WHEN OTHERS => % END CASE ; END PROCESS ; ' i END ASMArch ; i EEL 4930/5934 Reconfigurable Computing Midterm Exam — Spring Semester 2010 Name (a) Based on the VHDL code from the previous page complete the following timing diagram for state, Eny, and Ean. Clock 1 I, state E . i Resetniiiiiiiii::: Goiiiéti“‘iii g EnY : : , : _ : : : : z : - - — — — . — — -- I --~-—:-—--—-l I --—- l I I ‘I ‘ ' ' ' ' ' ' ' " n I ”"“|""" - ""‘I’"“'F““'T"_" é: Eflzunn , .... -1 .... ' i ____ __ l l i .... -3 ‘ (3) Based on the VHDL code from the previous page, complete the corresponding ASM chart using state boxes, conditional outputs, etc. State 00 l l i l l l g i g, E l i l l EEL 4930/5934 Reconfigurable Computing Midterm Exam — Spring Semester 2010 6- Name FPGA confi uration block details. Specify the portion of the bit stream (Althrough I) required to program a Virtex slice to implement the logic circuits specified in following VHDL statements: Y <= (G4 AND GB) OR ((NOT GZ) AND G1); IF (CLK’EVENT AND CLK ='1’) THEN xo <= (F3 AND F2)I(NOT F1); IMPORTANT NOTE: For “don’t care” values, be sure to use ‘X’ instead of ‘0‘ or ‘1’. A B CV5? F 6W... rest of bit stream a . . LUT1[012 3 4 5 6 78 9101112131415] lfilJalagdalgkolfield/DVD?” LUT2 9 10 11 12 13 14 15] [31221236331336 loVLal/Tfl Definition of MUXs . x ZVXZ: Ffirfzvrf/ i g 3 i i i i 1 E 3 EEL 4930/5934 Reconfigurable Computing Midterm Exam — Spring Semester 2010 ENTITY _entity_name IS PORT(__input_name, _input_name _input_vector_name _bidir_name, _bidir__name _output_name, _output_name END _entity_name; ARCHITECTURE 3 OF _entity_name IS SIGNAL _signal_name : STD_LOGIC; SIGNAL _signal_name : STD_LOGIC; BEGIN -- Process Statement —— Concurrent Signal Assignment —— Conditional Signal Assignment -- Selected Signal Assignment -- Component Instantiation Statement END a; Name :IN STD_LOGIC; : IN STD_LOGIC_VECTOR(__high downto _low); : INOUT STD_LOGIC; : OUT STD_LOGIC); _instance_name: _component_name PORT MAP (_component_port => _connect_port, WITH _expression SELECT _component_port => _connect_port); _signal <= _expression WHEN _constant__value, _expression WHEN _constant_value, _expression WHEN _constant_value, _expression WHEN _constant_value; _signal <= _expression WHEN _boolean_expression ELSE _expression WHEN _boolean_expression ELSE _expression; IF _expression THEN _statement; _statement; ELSIF _expression THEN _statement; _statement; ELSE _statement; _statement; END IF; CASE _expression IS WHEN _constant_value => _statement; _statement; WHEN _constant_value => _statement; _statement; WHEN OTHERS => _statement; _statement; END CASE; WAIT UNTIL _expression; <generate_label>: FOR <Ioop_id> IN <range> GENERATE -- Concurrent Statement(s) END GENERATE; ...
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This note was uploaded on 03/27/2012 for the course EEL 4930 taught by Professor Staff during the Spring '08 term at University of Florida.

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MidtermSpring2010Solution - EEL 4930/5934 Reconfigurable...

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