codesynthesis - VHDL to circuit mappings for comment...

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Unformatted text preview: VHDL to circuit mappings for comment constructs and circuit types Fall 2007 Caveats: Synthesis software may optimize the circuit down to something that looks different, but it should function the same. In addition, subtle changes to the code can sometimes dramatically change the hardware mapping or even make a hardware mapping impossible. Except where noted to the contrary, all labels used in expressions or assignments are for one bit signals of type std_logic. Behavioral constructs: Latches: (not recommended) -- if/then/endif processéir Ajay} if(A = ‘1’) then B <= C; end if; end process; processofi’ iii—m} if(A = ‘1’) then B <= ‘0’; end if; end process; -- if/then/endif with -- more complex condition expression processz if; it 3; g7 if (C and D) or not (B B <=_ A; end if; end process; lof2 VHDL to circuit mappings for comment constructs and circuit types Fall 2007 -- if/then/endif with -- more complex expression for value @ processg AjCj g, A“, $3.} if(A = ‘1’)theny B <= (C and D) or not (B and F); end if; end process; Latch with reset: (not recommended) K; L A processé if (RST = ‘1’) then A <= ‘0’; elsif (ENA = ‘1’) then A <= B; end if; end process; Combinational logic using if/then/else/end if A process(«§g A? (a? " if(A=‘1’)then B <= C; else B <= ‘0’; end if; end process; --if then/else/end if B» -- with more complex -- input expressions . a} M) if(A= E) and (F = ‘1’) then B <= C and D; else B <= G or H; end if; end process; 20f2 VHDL to circuit mappings for comment constructs and circuit types Fall 2007 if/then/elsif structures (just a few samples) process(A,C,D,G,H) if(A = ‘0’) then A B <= C; elsif (D = ‘1’) then B <= G or H; else B B <= ‘0’; end if; end process; process(A,C,D,E,G,H,I,J,K) E A if(A = ‘0’) then 7‘ B <= C; elsif (D = ‘1’) then B <= G or H; e1sif(E = ‘0’) then B <= I xor J; else B <= K; end if; end process; process(A,C,D) if (A = ‘0’) then if(C = ‘1’) then B <= D; else B <= ‘0’; end if; else B <= ‘1’; end if; end process; 3of6 VHDL to circuit mappings for comment constructs and circuit types Fall 2007 more if/then/elsif structures process(A,C,D,E,F,G) E if(A = C) then m ’ B <= C; ‘ elsif (A = ‘ 1 ’ and D = E) then B <= F and G; elsif (A & D) = “01” then ‘f ' B <= F xor G; elsif E = A then B <= F xor G; else B <= ‘ 1 ’; end if; end process; process(A,C,D,E,F,G) if (A = C) then B <= C; elsif (A = ‘ 1 ’ and D = B) then B <= F and G; elsif (A & D) = “01” then B <= F xor G; elsif E = A then B <= F xor G; end if; end process; -- the same one as previous with default -- value given for B process(A,C,D,E,F,G) B <= ‘1’; if (A = C) then ( ‘ f B<=C; {fit elsif(A=‘1’andD=E)then “w! I N a B <= F and G; i’ f KL, . l K e1sif(A & D) = “01” then (I; “if; x B <= F xor G; l, elsif E = A then B <= F xor G; end if; end process; 4of6 VHDL to circuit mappings for comment constructs and circuit types Fall 2007 For loops let A, B, and C be signals of type stdfllogic_vector(3 downto 0) other unspecified signals are std_logic type process(A,C) 3(5)) , N.“ a \ fori in 0 to 3 loop 13(1) <=A(1) xor 0(1); , if) -. _w<,..e J end 100p; via-«(i W“ end recess; in?” v ‘ NE ( ;5 g, urn-um mewvv ‘ -- let x be a signal of type integer —— for which the value is not constant process(A,C) fori in 0 to x loop B(i) <= A(i) xor C(i); end loop; 3 e end process; W -- loop using variable to carry value from if k in»; . . ,‘ j Mn t -- one 1terat1on to the next if} f?‘\ 2k é process() mg m, ' i g ‘ . ' . ‘6‘ ‘ “fix variable M. std_logic, figll‘ J} 2‘ ‘it xx; A) M := ‘0’; ” ’ / ' W foriin1t03loop 55}? > 3 M := A(i) xor M; E - I end loop; D <= M; end process; —- loop with nested if/then/else process(A,C) ,9 for i in 0 tO/Iloop if(D = ‘0’) then B(i) <= A(i) xor C(i); else B(i) <= A(i) and C(i); end loop; end process; VHDL to circuit mappings for comment constructs and circuit types Fall 2007 Registers and Flip—Flops using if/then structures A, B, C are signals of type std_logic_vector(3 downto 0) other signals are std__logic process(CLK) if (fising_edge(CLK) then B <= A; end if end process; process(CLK,nRST) if (nRST = ‘0’) then B <= (others => ‘0’); elsif (rising_edge(CLK) then B <= A; end if end process; process(CLK,nRST,nSET) if (nRST = ‘0’) then B <= (others => ‘0’); elsif (nSET = ‘0’) then B <= (others => ‘1’); elsif (rising_edge(CLK) then B <= A; end if end process; -—OOPS! process(CLK,nRST) if (nRST = ‘0’) then B <= (others => ‘0’); elsif (rising_edge(CLK)) then B <= A; else B <= ‘1’; end if end process; 6of6 ...
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This note was uploaded on 03/28/2012 for the course ECE 337 taught by Professor J during the Fall '09 term at Purdue University-West Lafayette.

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codesynthesis - VHDL to circuit mappings for comment...

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