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ECE337 Spring 2007

ECE337 Spring 2007 - ECE337 Spring 2007 Code for block...

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ECE337 Spring 2007, Code for block diagram drawing example -- Customer ticket counter such as used at drivers license bureau -- UPSW, DNSW = inputs from 16 "up" buttons and 16 "down" buttons -- SEGS1, SEGS2 = two digit 7-segment display outputs entity ServiceCounter is port(UPSW, DNSW: in std_logic_vector(15 downto 0); CLK, RST: in std_logic; SEGS1, SEGS2; out std_logic_vector(6 downto 0)); end ServiceCounter; architecture mixed of ServiceCounter is signal upsw1,upsw2,dnsw1,dnsw2: std_logic_vector(15 downto 0); signal upedge,dnedge: std_logic_vector(15 downto 0); signal upcnt,dncnt,upreq,dnreq,upcy,dncy: std_logic; signal dig1,dig2: std_logic_vector(3 downto 0); -- Be sure to look at the source code for this component component UpDnCounter port(up,dn,clk,rst: in std_logic; cnt: out std_logic_vector(3 downto 0); cyover, cyunder: out std_logic); end component; Is this blockcombinational? -- Source code omitted component Decode7Seg port(bin: in std_logic_vector(3 downto 0); segs: out std_logic_vector(6 downto 0)); end component; -- source code omitted component or16 port(i: in std_logic_vector(15 downto 0); o: out std_logic); end component;
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