ece337p5 - RTL Design Using Block Diagrams 10/24/2011 1 RTL...

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10/24/2011 1 RTL Design Using Block Diagrams
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2 10/24/2011 RTL Design Register Transfer Level (review) Most VHDL or Verilog is written this way A “register-centric” view. Design consists entirely of: Registers (usually edge sensitive FFs) Movement of data into, out of, or between registers (busses, wires, multiplexers) Modification of data as it moves between registers (combinational logic) You should approach final project this way Labs 4-6 design approach is RTL FYI: some designers & texts restrict RTL to purely structural & dataflow design
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3 10/24/2011 RTL Block Diagrams Blocks must represent… A register Combinational logic A sequential function that can be easily partitioned into registers or combinational logic – such as state machine counter A lower level block diagram Can also include common schematic elements (gates, flip-flops) only if needed to improve readability Difference between block diagram & schematic (in ECE337) Schematic will show individual logic gates or common functions such as multiplexers, full-adders, decoders,. .. RTL block diagram will usually lump closely related combinational logic into a single block. May show some common logic functions such as multiplexers, etc.
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4 10/24/2011 Schematic Guidelines Allowable symbols: Register, flip-flop, latch Multiplexer, Decoder Adder, Multiplier, Comparator, etc. All common logic gates: and, or, xor, nand, … Use bubble to indicate inverted input or output Use #/ to indicate multiple bits Can specify multiple bit versions of functions Flow left->right, top->down as much as possible Use arrows if necessary to indicate flow Apply also to RTL Block diagrams
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5 10/24/2011 Schematic Guidlines reg 16 16 reg mux 2 dec 2 rst rst d q rst d q rst en
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6 10/24/2011 Schematic Guidelines Common arithmetic & comparison operations a+b a b cin s cout a>b a b q 16 16 Common logical operations (some pins may be inverted) 16 16 16 16 16
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7 10/24/2011 Small Example (detailed) 1MHz to 10Hz clock divider with enable & reset what coding style would you use for each block? reg 17 17 rst x+1 17 if 100k then 0 else x x mux ena 17 17 cnt nextcnt 17 1 10Hz pulse clk How many processes would you use to code this? What would each process implement?
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8 10/24/2011 Small Example (less detail) reg 17 17 rst increment cnt nextcnt 17 1 10Hz clk Output Logic ena enough detail for most purposes
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9 10/24/2011 Small Example (block) 100k Clock Divider rst ena clk 10Hz pulse to use in higher level diagrams
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An approach to block diagram Identify inputs & outputs What are the required functions? What is the sequence of operation? This often describes the main state machine/control unit If possible, start with a known similar design & adapt it The diagram will often consist of: control unit state machine counters/timers to help the control unit functional units that implement operations to be performed by the system In ECE437 you will learn another approach - pipelining 10 10/24/2011
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11 10/24/2011
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This note was uploaded on 03/28/2012 for the course ECE 337 taught by Professor J during the Fall '09 term at Purdue University-West Lafayette.

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ece337p5 - RTL Design Using Block Diagrams 10/24/2011 1 RTL...

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