2 10/24/2011 RTL Design Register Transfer Level (review) Most VHDL or Verilog is written this way A “register-centric” view. Design consists entirely of: Registers (usually edge sensitive FFs) Movement of data into, out of, or between registers (busses, wires, multiplexers) Modification of data as it moves between registers (combinational logic) You should approach final project this way Labs 4-6 design approach is RTL FYI: some designers & texts restrict RTL to purely structural & dataflow design
3 10/24/2011 RTL Block Diagrams Blocks must represent…A register Combinational logic A sequential function that can be easily partitioned into registers or combinational logic –such as state machine counter A lower level block diagram Can also include common schematic elements (gates, flip-flops) only if needed to improve readability Difference between block diagram & schematic (in ECE337) Schematic will show individual logic gates or common functions such as multiplexers, full-adders, decoders,... RTL block diagram will usually lump closely related combinational logic into a single block. May show some common logic functions such as multiplexers, etc.
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