p1 - 1 Here is a brief summary. See module 2 ASIC Design...

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Unformatted text preview: 1 Here is a brief summary. See module 2 ASIC Design Process for more detail Block Diagram (HDL Designer from Mentor Graphics) draw a schematic containing a block for each major subsystem of your design and add wires to show how they are connected. 2 VHDL Code write VHDL source code describing the required behavior of each subsystem or subcircuit. Simulation (Modelsim from Mentor Graphics) debug your code. It is in some ways similar to source code debuggers you may have used (i.e., you can set breakpoints, watch variables, etc) except that you can also display waveforms for the inputs and outputs of your design. Synthesis (Design Compiler from Synopsys) takes your source code, figures out what logic gates and storage elements are needed to make a circuit out of it. The output is a netlist, i.e., a list of logic circuits and the connections between them. Place and Route (SOC Encounter from Cadence) takes the netlist that came from synthesis and produces a complete silicon layout from it. The layout shows graphically where all of the transistors and wires are supposed to go during manufacturing. Timing (Pathmill from Synopsys) identifies timing problems (setup and hold violations) and determines the maximum clock rate for the IC layout that was produced. Note: there are several additional layout verification steps not described in this figure. Fabrication (not enough time to do in one semester) send the layout data and chip packaging specifications to a fabrication company to manufacture the chip. Real word after fabrication, you would need to test the chips. Only a small subset of VHDL syntax can actually be used for circuit design. A large portion of the language is targeted exclusively for simulation modeling and design verification. 3 Even within the allowable subset of VHDL syntax, there are severe restrictions on how you can write your code and still expect it to translate into hardware in a predictable manner. In this class, we will focus almost exclusively on the type of code needed to create a circuit design. We will cover a small amount of additional syntax to make it easier to write test benches for verifying your design. Definition: Test Bench: code that is written specifically for the purpose of generating test waveforms for input to a simulation of your VHDL designs. Test Benches can also be used to automatically check outputs of your designs. Later in the semester, your teaching assistants will use specialized test benches to evaluate your designs. 1. Before writing VHDL code, think very hard about how you would build the circuit first. Try to write your code in a way that describes, as directly as possible, the behavior of each part of the circuit....
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This note was uploaded on 03/28/2012 for the course ECE 337 taught by Professor J during the Fall '09 term at Purdue University-West Lafayette.

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p1 - 1 Here is a brief summary. See module 2 ASIC Design...

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