p4 - ECE 337 Spring 2007 1 ASIC Design Process ECE 337 -...

Info iconThis preview shows pages 1–7. Sign up to view the full content.

View Full Document Right Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: ECE 337 Spring 2007 1 ASIC Design Process ECE 337 - ASIC Design Lab ECE 337 Spring 2007 2 ASIC Design Process with VHDL Design Flow VHDL Design Block Diagram Simulation Synthesis Place & Route VHDL or Verilog Code Block Diagram Synthesis Simulation Simulation Place & Route Fabrication (not going to do in ECE 337) Timing Cadence or HDLDP Modelsim Modelsim Cadence Cadence Synopsys MOSIS netlist netlist masks netlist ECE 337 Spring 2007 3 Where To Start? Read and understand the project specification Conceptualize and visualize the design Block Diagrams Flowcharts State Transition Diagrams Truth Tables and K- maps Coding (use VHDL or Verilog) You might want to use Cadence or HDL Designer Pro to create structural code (block diagram) VHDL or Verilog Code Block Diagram Synthesis Simulation Simulation Place & Route Fabrication (not going to do in ECE 337) Timing Modelsim Cadence Synopsys Modelsim Cadence MOSIS netlist netlist Cadence or HDL Designer ECE 337 Spring 2007 4 After Coding Create test bench to test your design Simulate your code using the test bench and verify that the source version behaves correctly (we are using Modelsim in ECE337 for this task) VHDL or Verilog Code Block Diagram Synthesis Simulation Simulation Place & Route Fabrication (not going to do in ECE 337) Timing Modelsim Modelsim Cadence Cadence Synopsys MOSIS netlist netlist masks netlist Cadence or HDLDP ECE 337 Spring 2007 5 Creating a test bench We have a script to create the template code for a test bench called tbgen You can supply options to the script to generate a test bench template that is suitable for your design (e.g. for sequential designs, use the s option etc.) ECE 337 Spring 2007 6 Creating a test bench...
View Full Document

Page1 / 17

p4 - ECE 337 Spring 2007 1 ASIC Design Process ECE 337 -...

This preview shows document pages 1 - 7. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online