p8 - Static CMOS Standard Cell CMOS Logic and Layout 1 Why...

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10/24/2011 1 Static CMOS Standard Cell, CMOS Logic, and Layout
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10/24/2011 Why spreadsheets aren‟t enough Chip-level specification needs a new emphasis By George Janac, EEdesign.com Mar 26, 2004 (7:00 PM EST) URL: http://www.eedesign.com/article/showArticle.jhtml?articleId=18402919 … the preferred mode of early chip estimation and analysis is still the financial modeling application software spreadsheets. Engineers continue to use them to analyze design estimates and forecasting, and for project management. That's because no single system has been capable of giving chip architects, engineers and managers timely information about how a design will behave in a production process, starting from the specification level. Not much has changed in 30 years. Specifications for complex chip designs still start on a napkin or a piece of paper. They are refined on whiteboards, in documents or in presentation systems. These crude specifications are then transferred to spreadsheets for estimation. Getting information on the right IP, behavior of standard cell library, and features of memories represent a massive data collection challenge for managers and architects. Often, there is only a modicum of understanding of what can be realistically expected of a design in production. Inconceivably, multi-million dollar projects have been scrapped after six months when the management team realized the design specified on a napkin would produce a bad yield, burn the package or worse. Spreadsheet analysis is no longer sufficient. Early initial guesses often become nails in the project coffin.
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10/24/2011 3 Standard Cell ASIC and alternatives.
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4 10/24/2011 What is a Standard Cell ASIC? Standard cell approach Library of pre-designed logic “cells” Synthesis (or you) decide which cells to use Makes design relatively easy vs. full custom Cells designed to stack vertically & horizontally Place & Route (layout) software positions and connects cells Chips are expensive in small quantities Cheap in large quantities Changes to chip are expensive This is what you have been doing ABET Outcome
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5 10/24/2011 A trivial but complete layout bonding pad VSS pad Clk pad Vdd pad input pad Why might you leave I/O pads out on purpose when designing something like the UART or I2C interface? corner cell filler cell
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6 10/24/2011 shared vdd rail I/O Pin (Not an I/O pad!) row of standard cells vertical routing metal 2 horizontal routing metal 3 a transistor
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7 10/24/2011 Full-custom ASIC draw transistor schematics, lay out mask by hand allows best area/speed optimization takes longer & more expensive to design harder to re-use design for other technologies Also cheap in large quantities Mixing Full Custom & Standard Cell Design some blocks full custom (e.g. cache & data path) where speed is most critical Common for large systems on a chip (SOC) ABET Outcome Std. Cell vs Other Approaches
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8 10/24/2011 FPGAs or CPLDs FPGA = Field Programmable Gate Array CPLD = Complex Programmable Logic Device
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p8 - Static CMOS Standard Cell CMOS Logic and Layout 1 Why...

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