{[ promptMessage ]}

Bookmark it

{[ promptMessage ]}


NI-Tutorial-5340 - Document Type Tutorial NI Supported Yes...

Info iconThis preview shows pages 1–3. Sign up to view the full content.

View Full Document Right Arrow Icon
1/7 www.ni.com LabVIEW FPGA Design for Code Modules (IP Cores) 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. Overview This document helps engineers and developers using the NI LabVIEW FPGA Module to build reusable, scalable, and maintainable code modules, also called intellectual property (IP) cores, IP blocks, or field-programmable gate array (FPGA) functions. Learn about recommended component design techniques, based on your application and optimization needs, that can help you reuse IP more efficiently and effectively among applications and developers. Table of Contents IPNet FPGA Guidelines at a Glance FPGA IP – Reusable Code Modules General LabVIEW Style Guide Scalable IP Internal Data Storage Timing Independence Project Independence I/O Module Independence Performance Documentation, Testing, and Examples Summary IPNet FPGA Guidelines at a Glance Scalable IP Scalable IP should allow for multiple blocks to be used together to access increasing amounts of I/O or required memory Internal Data Storage Feedback nodes access data points from previous iterations and pipelining VI scoped dual port memory and FIFOs allow for FPGA memory access without the use of the LabVIEW Project Timing Independence Avoid Using loop structures. Use loops outside of IP Block Do not using timing functions to delay the IP Block : Document Type Tutorial : Yes NI Supported : Dec 3, 2010 Publish Date
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
2/7 www.ni.com Project Independence IP should not require the configuration in the project Avoid using the FPGA wizard I/O Module Independence Access I/O Nodes from the calling VI Or use the FPGA I/O constant to address a module and channel. Performance Pipelining is the use of feedback nodes or shift registers in order to allow items that would normally execute serially to execute in parallel The Single Cycle Timed Loop is a LabVIEW Timed Loop Structure used in LabVIEW FPGA. A SCTL allows for all the code within the loop to execute in one tick of the FPGA clock. FPGA IP – Reusable Code Modules Any software development effort includes the development of functions, subroutines, objects, code modules, or other basic building blocks of the larger architecture. As you design an application, you identify and implement individual functions and operations. Later on you can combine and integrate these building blocks to form the larger application. Through the process of developing different applications over time, a group or community of developers creates libraries of code modules representing common operations and reuses them to build future applications more quickly. The purpose of developing such libraries of code is to reduce the overall development effort by building and testing a function once and reusing it many times. Besides promoting the reuse of existing code, modular design also increases code testability and maintainability, so developers and designers can focus on application-specific features and code segments. The LabVIEW language has a set of guidelines used by programmers worldwide to develop subVIs that can be easily understood, applied in different applications, and maintained by different
Background image of page 2
Image of page 3
This is the end of the preview. Sign up to access the rest of the document.

{[ snackBarMessage ]}

Page1 / 7

NI-Tutorial-5340 - Document Type Tutorial NI Supported Yes...

This preview shows document pages 1 - 3. Sign up to view the full document.

View Full Document Right Arrow Icon bookmark
Ask a homework question - tutors are online