115 reviewer - exam2

115 reviewer - exam2 - COE115 exam2 reviewer Sunday,...

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PWM signal + RC lowpass filter s Disadvantages: dedicated timer for PWM, output needs to stabilize; Advantages: single output pin used Binary-weighted resistor circuit R-2R resistor ladder Analog comparator - Digital to analog conversion Conversion time - time from the start of a conversion until the result is availabl e. Upper bound on the maximum input frequency fmax = fs/2 To keep the input signal stable during conversion, a sample/hold stage is used. Analog to digital conversion - Analog-to-Digital / Digital-to-Analog COE115 exam2 reviewer Sunday, October 03, 2010 11:35 AM 1st Sem Page 1
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s Flash converter Digital ramp s u Similar to a tracking converter, but the counter resets to zero when analog input Tracking converter s Slope or Ratiometric ADC s s Delta-Sigma ADC Conversion techniques 1st Sem Page 2
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Successive approximation converter s - Z8 ADC 12 analog input sources Interrupt upon conversion complete Internal voltage reference generator DMA controller that can automatically initiate data conversion and transfer Operation 1st Sem Page 3
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160 consecutive clock cycles idle to power-down u u 40 clock cycles to power-up s Automatic power-down u Enable desired analog inputs by configuring the GPIO pins for alternate function Write to the ANAIN [3:0] field to select one of the 12 possible input sources r Clear CONT to 0 to select single shot r Write to the VREF bar bit to enable/disable the internal voltage reference generator r Set CEN to 1 to start conversion r Write to the ADC control register to configure ADC and begin conversion u CEN = 1 while conversion is in progress. 1 single shot conversion = 5129 system clock cycles u r 10-bit data result written to {ADCD_H[7:0], ADCD_L[7:6]} CEN = 0 r r Interrupt request sent to interrupt controller u When conversion is complete, ADC control logic performs: s Single-shot conversion u Enable desired analog inputs by configuring the GPIO pins for alternate function u Write to the ANAIN [3:0] field to select one of the 12 possible input sources r Clear CONT to 1 to select continuous conversion r Write to the VREF bar bit to enable/disable the internal voltage reference generator r Set CEN to 1 to start conversion r Write to the ADC control register to configure ADC and begin conversion u CEN = 1 while conversion is in progress. CEN resets to 0 to indicate first conversion is complete. CEN remains 0 for all subsequent conversion u An interrupt request is sent to interrupt controller to indicate conversion complete u Every 256 system clock cycles, 10-bit data result written to {ADCD_H[7:0], ADCD_L[7:6]} and an interrupt request for every complete conversion. u To disable conversion, CONT = 0 Continuous conversion ( The response of the ADC is limited by the input signal bandwidth and the latency of the ADC and its digital filter) s s ADC control register u CEN (0 = conversion complete, 1 = begin conversion) u Reserved = 0 u VREF bar (0 = internal voltage reference generator enabled, 1 = disabled)
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This note was uploaded on 03/22/2012 for the course ECON 1 taught by Professor Tuki during the Spring '12 term at CSU Pueblo.

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115 reviewer - exam2 - COE115 exam2 reviewer Sunday,...

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