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hwk 5 - Compare the results with Problem#1 3 Book problem...

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ECE 200 Digital Logic Systems Drexel University Fall 2011-2012 Homework #5 Due: Wednesday November 9th, 2009 at beginning of class (11:00AM) Show all work. Points will be removed for answers without work. Text problems are from Chapter 6.6 (p403) of the Marcovitz Text (3 rd Edition). It is your responsibility to do the correct problems if you are using a different edition of the book. Problems from different edition of the text will be marked incorrect. 1) Trace the following timing diagram for a SR latch 2) Trace the above timing diagram for a S’R’ Latch (treat S as S’ and R as R’).
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Unformatted text preview: Compare the results with Problem #1 3) Book problem 6-2. Trace the problem through and find the truth table for: a) the original NOR circuit b) the NAND circuit you design 4) For the timing diagram below, draw the output response for a positive edge-triggered FF R S Q 5) For the same timing diagram used in problem #4, using CLK as C, draw the output of a D Latch. Perform the same task, now using CLK’ as C. How do these results compare to Problem #4. CLK D Q CLK...
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