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Unformatted text preview: Compare the results with Problem #1 3) Book problem 6-2. Trace the problem through and find the truth table for: a) the original NOR circuit b) the NAND circuit you design 4) For the timing diagram below, draw the output response for a positive edge-triggered FF R S Q 5) For the same timing diagram used in problem #4, using CLK as C, draw the output of a D Latch. Perform the same task, now using CLK’ as C. How do these results compare to Problem #4. CLK D Q CLK...
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- Spring '08
- Logic gate, CLK, timing diagram, Flip-flop