Lecture #5 - Characteristics of logic gates, noise margin, fanout

Lecture #5 - Characteristics of logic gates, noise margin, fanout

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ECE 301 – Digital Electronics Electrical and timing characteristics of logic gates, Noise margin, and Fanout
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Learning Objectives Representing logic levels (using voltages) Characteristics of logic gates Electrical Timing Constraints on digital logic circuit design Noise margin Fan-out Spring 2012 ECE 301 - Digital 2
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Reading Supplemental Spring 2012 ECE 301 - Digital 3
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Electrical Characteristics of Logic Gates Spring 2012 ECE 301 - Digital 4
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Logic Gates Logic gates are the basic building blocks for combinational and sequential logic circuits. They are, however, abstractions. Spring 2012 5 ECE 301 - Digital
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Logic Gates In fact, as we have already seen, logic gates are electrical circuits. Spring 2012 6 ECE 301 - Digital
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Logic Gates As such, the logic levels must be represented using an electrical signal. Most technologies use voltages to represent the logic levels. TTL CMOS Some, but very few, technologies use currents to represent the logic levels. Spring 2012 7 ECE 301 - Digital
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Representing Logic Levels Ideally, a single voltage level is specified for each logic level. VDD (supply voltage) → logic 1 GND (0 V) → logic 0 Logic 1 = high voltage Logic 0 = low voltage Spring 2012 8 ECE 301 - Digital
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Representing Logic Levels In reality, a range of voltages is specified for each logic level. GND VDD V1,MIN V0,MAX Logic 1 Logic 0 Undefined Threshold voltages Spring 2012 9 ECE 301 - Digital
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Furthermore, voltage ranges for logic 0 and logic 1 are specified for both the input and output of a logic gate. They are defined in terms of four parameters: VOH = output high voltage VIH = input high voltage VOL = output low voltage VIL = input low voltage These are specified in the data sheet.
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Lecture #5 - Characteristics of logic gates, noise margin, fanout

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