chap04_1 - Advanced Computer Architecture Prof Thriveni T K...

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Advanced Computer Architecture Prof Thriveni T K Hwang, Chapter 4 Processors and Memory Hierarchy 4.1 Advanced Processor Technology
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Design Space of Processors Processors can be “mapped” to a space that has clock rate and cycles per instruction (CPI) as coordinates. Each processor type occupies a region of this space. Newer technologies are enabling higher clock rates. Manufacturers are also trying to lower the number of cycles per instruction. Thus the “future processor space” is moving toward the lower right of the processor design
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CISC and RISC Processors Complex Instruction Set Computing (CISC) processors like the Intel 80486, the Motorola 68040, the VAX/8600, and the IBM S/390 typically use microprogrammed control units, have lower clock rates, and higher CPI figures than… Reduced Instruction Set Computing (RISC) processors like the Intel i860, SPARC, MIPS R3000, and IBM RS/6000, which
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Superscalar Processors This subclass of the RISC processors allow multiple instructoins to be issued simultaneously during each cycle. The effective CPI of a superscalar processor should be less than that of a generic scalar RISC processor. Clock rates of scalar RISC and superscalar RISC machines are similar.
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VLIW Machines Very Long Instruction Word machines typically have many more functional units that superscalars (and thus the need for longer – 256 to 1024 bits – instructions to provide control for them). These machines mostly use microprogrammed control units with relatively slow clock rates because of the need to use ROM to hold the microcode.
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Superpipelined Processors These processors typically use a multiphase clock (actually several clocks that are out of phase with each other, each phase perhaps controlling the issue of another instruction) running at a relatively high rate. The CPI in these machines tends to be relatively high (unless multiple instruction issue is used). Processors in vector supercomputers are mostly superpipelined and use multiple
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Instruction Pipelines Typical instruction includes four phases: fetch decode execute write-back These four phases are frequently performed in a pipeline, or “assembly line” manner, as illustrated on the next slide (figure 4.2).
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Instruction pipeline cycle – the time required for each phase to complete its operation (assuming equal delay in all phases) Instruction issue latency – the time (in cycles) required between the issuing of two adjacent instructions Instruction issue rate – the number of instructions issued per cycle (the degree of a superscalar) Simple operation latency – the delay (after the previous instruction) associated with the completion of a simple operation (e.g. integer add) as compared with that of a complex operation (e.g. divide). Resource conflicts – when two or more instructions
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chap04_1 - Advanced Computer Architecture Prof Thriveni T K...

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